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我們的最新職缺均詳列在智原官網及104 人力銀行。

請透過以下方式應徵：. - 在智原官網填寫資料並上傳履歷. 加入智原 智原提供絕佳的機會給希望得到更富挑戰性工作的人才。

我們的最新職缺均詳列在智原官網及104人力銀行。

請透過以下方式應徵： -在智原官網填寫資料並上傳履歷 -在104人力銀行應徵 -將您的履歷投遞至：[email protected] 請直接勾選有興趣的徵才職務，再按職缺列表下方的"填寫履歷"進入第二步驟，填寫相關資料並送出即完成履歷登錄。

職缺列表 瀏覽全部職缺 職缺筆數：86筆 職務名稱 徵才條件 工作地點 RDTestChip&IPManagementEngineer(約聘) 1. ResponsibleforRDtestchiplogisticmanagement(includingstorage&forecastcontrol) 2. ResponsibleforIPinformationmaintain&support 3. ResponsibleforRD/IPdatacollection&report 其他條件:1.MicrosoftOffice(Word,Excel,PowerPoint) 2.工作技能：了解FoundryMPWshuttle運作 新竹 SeniorGiga-bitsEthernetPHYAnalogDesignEngineer/PrincipalEngineer 熟悉Giga-bitsEthernetPHYanalogdesign,systemoperation,Voltage-modedriver,Receiveranalogfront-end其他條件:1.10/100/G-PHYdesign&productionexperienceor PipelineADCDesign 2.CapabletocommunicateinEnglishisastrongplus 新竹 Sigma-deltaADC/DAC/AudioCODECManager/Designer 1.Sigma-deltaADC/AudioCODECdesign 2.Teamleader/management其他條件:1.MSorDoctoratedegreeinEErelated 2.5年以上相關工作經驗 新竹 EmbeddedSoftwareEngineer 1.EmbeddedSystemIP/FPGAVerification 2.SWProgramming(CPU/USB/PCIeIPverification.Kernel/driverporting)其他條件:1.對EmbeddedSystem,Linux,ARMSOC有興趣2.高度學習熱忱，相關經驗尤佳 新竹 ASICConsultantManager-台南 1.Responsibleforthemaintechnicalcontactwindowand consultantofchipimplementationfromRTL-in/netlist-into tapeoutforASICcustomers 2.ResponsibleforASICprojectmanagementandcoordinationamong internalsupportinggroups 3.ResponsibleforDFTimplementation,includingMBIST,Scan insertion,IOleveltesting,JTAGandATPGgeneration 4.ResponsibleforASICconstraintvalidation,including floorplan,timing,clock,package,power,andsoon. 其他條件:1.Experiencedinadvancednodeprocessisaplus 2.Experiencedinchipdesignflowandchipimplementationflow 3.FamiliarwithEDAtoolsincludingPrimeTime,Debussy,Verilog-XL,DesignCompiler,andformalverificationtools 4.FamiliarwithDFTrelatedflowandutilitiesisaplus 5.Interestedincommunicatingwithpeople 6.Experiencedinmanagementisaplus 7.TraininginHsinchuHQatleast3months,dependingontrainingresulttorelocateinTainan 台南 SOCPhysicalDesignManager-花蓮 1.ResponsibleforASICphysicalimplementationbyusingautomaticplaceandroutetools.TheP&Rprocessesincludingfloorplanning,powerplansynthesisandanalysis,physicaltimingoptimization,clocktreesynthesis,routing,andpost-routingoptimizations. 2.ResponsibleforphysicalverificationincludingDRC,LVSandESDchecking.其他條件:1.Experiencedinadvancednodeprocessisaplus 2.BSorMSdegreeinEEorCSrelated 3.ExperiencedinCadenceInnovusfloworSynopsysICC2flow 4.Experiencedinhierarchicalimplementation,timingclosure,IRdropanalysis,crosstalkanalysisisaplus 5.Experiencedinphysicalverificationandlayouteditingisaplus 6.Experiencedinmanagementisaplus 7.TraininginHsinchuHQatleast3months,dependingontrainingresulttorelocateinHualien 其他 LogicDesignFlowCADEngineer 1.Front-enddesignflowdevelopment 2.LogicSynthesis,STA,LEC,ECOflowcreationandconsultant其他條件:1.Familiarwithscriptlanguage(ex.,TCL,Perl) 2.ExperienceofuseSoCdesigntiminganalysis,logicsynthesisisaplus 新竹 ASICConsultantEngineer-花蓮 1.Responsibleforthemaintechnicalcontactwindowand consultantofchipimplementationfromRTL-in/netlist-into tapeoutforASICcustomers 2.ResponsibleforASICprojectmanagementandcoordinationamong internalsupportinggroups 3.ResponsibleforDFTimplementation,includingMBIST,Scan insertion,IOleveltesting,JTAGandATPGgeneration 4.ResponsibleforASICconstraintvalidation,including floorplan,timing,clock,package,power,andsoon. 其他條件:1.Experiencedinadvancednodeprocessisaplus 2.Experiencedinchipdesignflowandchipimplementationflow 3.FamiliarwithEDAtoolsincludingPrimeTime,Debussy,Verilog-XL,DesignCompiler,andformalverificationtools 4.FamiliarwithDFTrelatedflowandutilitiesisaplus 5.Interestedincommunicatingwithpeople 6.TraininginHsinchuHQatleast3months,dependingontrainingresulttorelocateinHualien 其他 SPICE/PDKCAD工程師 1. 建構類比IC開發流程與PDK維護 2. Spicemodel環境建構與不同foundryPPAsupport 其他條件:1. 熟悉C/C++,TCLscrpit. 2. 熟悉simulationtool:Hspice/Spectre/Finesim.. 3. 熟悉Virtuosotool 新竹 ASICConsultantEngineer-台南 1.Responsibleforthemaintechnicalcontactwindowand consultantofchipimplementationfromRTL-in/netlist-into tapeoutforASICcustomers 2.ResponsibleforASICprojectmanagementandcoordinationamong internalsupportinggroups 3.ResponsibleforDFTimplementation,includingMBIST,Scan insertion,IOleveltesting,JTAGandATPGgeneration 4.ResponsibleforASICconstraintvalidation,including floorplan,timing,clock,package,power,andsoon. 其他條件:1.Experiencedinadvancednodeprocessisaplus 2.Experiencedinchipdesignflowandchipimplementationflow 3.FamiliarwithEDAtoolsincludingPrimeTime,Debussy,Verilog-XL,DesignCompiler,andformalverificationtools 4.FamiliarwithDFTrelatedflowandutilitiesisaplus 5.Interestedincommunicatingwithpeople 6.TraininginHsinchuHQatleast3months,dependingontrainingresulttorelocateinTainan 台南 1 2 3 4 5 6 7 8 9 有任何相關問題請與智原科技人力資源單位聯絡 Tel:+886-3-5787888#88983