Sequential Logic Circuits and the SR Flip-flop

A basic NAND gate SR flip-flop circuit provides feedback from both of its outputs back to its opposing inputs and is commonly used in memory circuits to store a ... X Registertodownloadpremiumcontent! Registertodownloadpremiumcontent! X Deutsch Polski Register LogIn ACCircuits Amplifiers Attenuators BinaryNumbers BooleanAlgebra Capacitors CombinationalLogic Connectivity Counters DCCircuits Diodes Electromagnetism Filters Inductors Input/OutputDevices LogicGates MiscellaneousCircuits OperationalAmplifiers Oscillator PowerElectronics PowerSupplies Premium RCNetworks Resistors Resources SequentialLogic Systems Transformers Transistors WaveformGenerators PremiumContent FurtherEducation Sitemap ContactUs Home / SequentialLogic / SequentialLogicCircuits SequentialLogicCircuits SequentialLogicCircuitsuseflip-flopsasmemoryelementsandinwhichtheiroutputisdependentontheinputstate UnlikeCombinationalLogiccircuitsthatchangestatedependingupontheactualsignalsbeingappliedtotheirinputsatthattime,SequentialLogiccircuitshavesomeformofinherent“Memory”builtin. Thismeansthatsequentiallogiccircuitsareabletotakeintoaccounttheirpreviousinputstateaswellasthoseactuallypresent,asortof “before”and“after”effectisinvolvedwithsequentialcircuits. Inotherwords,theoutputstateofa“sequentiallogiccircuit”isafunctionofthefollowingthreestates,the“presentinput”,the“pastinput”and/orthe“pastoutput”.SequentialLogiccircuitsremembertheseconditionsandstayfixedintheircurrentstateuntilthenextclocksignalchangesoneofthestates,givingsequentiallogiccircuits“Memory”. SequentiallogiccircuitsaregenerallytermedastwostateorBistabledeviceswhichcanhavetheiroutputoroutputssetinoneoftwobasicstates,alogiclevel“1”oralogiclevel“0”andwillremain“latched”(hencethenamelatch)indefinitelyinthiscurrentstateorconditionuntilsomeotherinputtriggerpulseorsignalisappliedwhichwillcausethebistabletochangeitsstateonceagain. SequentialLogicRepresentation Theword“Sequential”meansthatthingshappenina“sequence”,oneafteranotherandinSequentialLogiccircuits,theactualclocksignaldetermineswhenthingswillhappennext.SimplesequentiallogiccircuitscanbeconstructedfromstandardBistablecircuitssuchas:Flip-flops,LatchesandCountersandwhichthemselvescanbemadebysimplyconnectingtogetheruniversalNANDGatesand/orNORGatesinaparticularcombinationalwaytoproducetherequiredsequentialcircuit. ClassificationofSequentialLogic Asstandardlogicgatesarethebuildingblocksofcombinationalcircuits,bistablelatchesandflip-flopsarethebasicbuildingblocksofsequentiallogiccircuits.Sequentiallogiccircuitscanbeconstructedtoproduceeithersimpleedge-triggeredflip-flopsormorecomplexsequentialcircuitssuchasstorageregisters,shiftregisters,memorydevicesorcounters.Eitherwaysequentiallogiccircuitscanbedividedintothefollowingthreemaincategories: 1. EventDriven – asynchronouscircuitsthatchangestateimmediatelywhenenabled. 2. ClockDriven – synchronouscircuitsthataresynchronisedtoaspecificclocksignal. 3. PulseDriven – whichisacombinationofthetwothatrespondstotriggeringpulses. Aswellasthetwologicstatesmentionedabovelogiclevel“1”andlogiclevel“0”,athirdelementisintroducedthatseparatessequentiallogiccircuitsfromtheircombinationallogiccounterparts,namelyTIME.Sequentiallogiccircuitsreturnbacktotheiroriginalsteadystateonceresetandsequentialcircuitswithloopsorfeedbackpathsaresaidtobe“cyclic”innature. Wenowknowthatinsequentialcircuitschangesoccuronlyontheapplicationofaclocksignalmakingitsynchronous,otherwisethecircuitisasynchronousanddependsuponanexternalinput.Toretaintheircurrentstate,sequentialcircuitsrelyonfeedbackandthisoccurswhenafractionoftheoutputisfedbacktotheinputandthisisdemonstratedas: SequentialFeedbackLoop ThetwoinvertersorNOTgatesareconnectedinserieswiththeoutputatQfedbacktotheinput.Unfortunately,thisconfigurationneverchangesstatebecausetheoutputwillalwaysbethesame,eithera“1”ora“0”,itispermanentlyset.However,wecanseehowfeedbackworksbyexaminingthemostbasicsequentiallogiccomponents,calledtheSRflip-flop. SRFlip-Flop TheSRflip-flop,alsoknownasaSRLatch,canbeconsideredasoneofthemostbasicsequentiallogiccircuitpossible.Thissimpleflip-flopisbasicallyaone-bitmemorybistabledevicethathastwoinputs,onewhichwill“SET”thedevice(meaningtheoutput=“1”),andislabelledSandonewhichwill“RESET”thedevice(meaningtheoutput=“0”),labelledR. ThentheSRdescriptionstandsfor“Set-Reset”.Theresetinputresetstheflip-flopbacktoitsoriginalstatewithanoutputQthatwillbeeitheratalogiclevel“1”orlogic“0”dependinguponthisset/resetcondition. AbasicNANDgateSRflip-flopcircuitprovidesfeedbackfrombothofitsoutputsbacktoitsopposinginputsandiscommonlyusedinmemorycircuitstostoreasingledatabit.ThentheSRflip-flopactuallyhasthreeinputs,Set,ResetanditscurrentoutputQrelatingtoit’scurrentstateorhistory. Theterm“Flip-flop”relatestotheactualoperationofthedevice,asitcanbe“flipped”intoonelogicSetstateor“flopped”backintotheopposinglogicResetstate. TheNANDGateSRFlip-Flop Thesimplestwaytomakeanybasicsinglebitset-resetSRflip-flopistoconnecttogetherapairofcross-coupled2-inputNANDgatesasshown,toformaSet-ResetBistablealsoknownasanactiveLOWSRNANDGateLatch,sothatthereisfeedbackfromeachoutputtooneoftheotherNANDgateinputs. Thisdeviceconsistsoftwoinputs,onecalledtheSet,SandtheothercalledtheReset,RwithtwocorrespondingoutputsQanditsinverseorcomplementQ(not-Q)asshownbelow. TheBasicSRFlip-flop TheSetState Considerthecircuitshownabove.IftheinputRisatlogiclevel“0”(R=0)andinputSisatlogiclevel“1”(S=1),theNANDgateY  hasatleastoneofitsinputsatlogic“0”therefore,itsoutputQmustbeatalogiclevel“1”(NANDGateprinciples).OutputQisalsofedbacktoinput“A”andsobothinputstoNANDgateXareatlogiclevel“1”,andthereforeitsoutputQmustbeatlogiclevel“0”. AgainNANDgateprincipals.IftheresetinputRchangesstate,andgoesHIGHtologic“1”withSremainingHIGHalsoatlogiclevel“1”,NANDgateYinputsarenowR=“1”andB=“0”.Sinceoneofitsinputsisstillatlogiclevel“0”theoutputatQstillremainsHIGHatlogiclevel“1”andthereisnochangeofstate.Therefore,theflip-flopcircuitissaidtobe“Latched”or“Set”withQ=“1”andQ=“0”. ResetState Inthissecondstablestate,Qisatlogiclevel“0”,(notQ=“0”)itsinverseoutputatQisatlogiclevel“1”,(Q=“1”),andisgivenbyR=“1”andS=“0”. AsgateXhasoneofitsinputsatlogic“0”itsoutputQmustequallogiclevel“1”(againNANDgateprinciples).OutputQisfedbacktoinput“B”,sobothinputstoNANDgateYareatlogic“1”,therefore,Q=“0”. Ifthesetinput,Snowchangesstatetologic“1”withinputRremainingatlogic“1”,outputQstillremainsLOWatlogiclevel“0”andthereisnochangeofstate.Therefore,theflip-flopcircuits“Reset”statehasalsobeenlatchedandwecandefinethis“set/reset”actioninthefollowingtruthtable. TruthTableforthisSet-ResetFunction State S R Q Q Description Set 1 0 0 1 SetQ»1 1 1 0 1 nochange Reset 0 1 1 0 ResetQ»0 1 1 1 0 nochange Invalid 0 0 1 1 InvalidCondition ItcanbeseenthatwhenbothinputsS=“1”andR=“1”theoutputsQandQcanbeateitherlogiclevel“1”or“0”,dependinguponthestateoftheinputsSorRBEFOREthisinputconditionexisted.ThereforetheconditionofS = R=“1”doesnotchangethestateoftheoutputsQandQ. However,theinputstateofS=“0”andR=“0”isanundesirableorinvalidconditionandmustbeavoided.TheconditionofS = R=“0”causesbothoutputsQandQtobeHIGHtogetheratlogiclevel“1”whenwewouldnormallywantQtobetheinverseofQ. Theresultisthattheflip-floploosescontrolofQandQ,andifthetwoinputsarenowswitched“HIGH”againafterthisconditiontologic“1”,theflip-flopbecomesunstableandswitchestoanunknowndatastatebasedupontheunbalanceasshowninthefollowingswitchingdiagram. S-RFlip-flopSwitchingDiagram Thisunbalancecancauseoneoftheoutputstoswitchfasterthantheotherresultingintheflip-flopswitchingtoonestateortheotherwhichmaynotbetherequiredstateanddatacorruptionwillexist.ThisunstableconditionisgenerallyknownasitsMeta-stablestate. Then,asimpleNANDgateSRflip-floporNANDgateSRlatchcanbesetbyapplyingalogic“0”,(LOW)conditiontoitsSetinputandresetagainbythenapplyingalogic“0”toitsResetinput.TheSRflip-flopissaidtobeinan“invalid”condition(Meta-stable)ifboththesetandresetinputsareactivatedsimultaneously. Aswehaveseenabove,thebasicNANDgateSRflip-floprequireslogic“0”inputstofliporchangestatefromQtoQandviceversa.Wecanhowever,changethisbasicflip-flopcircuittoonethatchangesstatebytheapplicationofpositivegoinginputsignalswiththeadditionoftwoextraNANDgatesconnectedasinverterstotheSandRinputsasshown. PositiveNANDGateSRFlip-flop AswellasusingNANDgates,itisalsopossibletoconstructsimpleone-bitSRFlip-flopsusingtwocross-coupledNORgatesconnectedinthesameconfiguration.ThecircuitwillworkinasimilarwaytotheNANDgatecircuitabove,exceptthattheinputsareactiveHIGHandtheinvalidconditionexistswhenbothitsinputsareatlogiclevel“1”,andthisisshownbelow. TheNORGateSRFlip-flop SwitchDebounceCircuits Edge-triggeredflip-flopsrequireanicecleansignaltransition,andonepracticaluseofthistypeofset-resetcircuitisasalatchusedtohelpeliminatemechanicalswitch“bounce”.Asitsnameimplies,switchbounceoccurswhenthecontactsofanymechanicallyoperatedswitch,push-buttonorkeypadareoperatedandtheinternalswitchcontactsdonotfullyclosecleanly,butbouncetogetherfirstbeforeclosing(oropening)whentheswitchispressed. Thisgivesrisetoaseriesofindividualpulseswhichcanbeaslongastensofmillisecondsthatanelectronicsystemorcircuitsuchasadigitalcountermayseeasaseriesoflogicpulsesinsteadofonelongsinglepulseandbehaveincorrectly. Forexample,duringthisbounceperiodtheoutputvoltagecanfluctuatewildlyandmayregistermultipleinputcountsinsteadofonesinglecount.Thenset-resetSRFlip-flopsorBistableLatchcircuitscanbeusedtoeliminatethiskindofproblemandthisisdemonstratedbelow. SRFlipFlopSwitchDebounceCircuit Dependinguponthecurrentstateoftheoutput,ifthesetorresetbuttonsaredepressedtheoutputwillchangeoverinthemannerdescribedaboveandanyadditionalunwantedinputs(bounces)fromthemechanicalactionoftheswitchwillhavenoeffectontheoutputatQ. Whentheotherbuttonispressed,theveryfirstcontactwillcausethelatchtochangestate,butanyadditionalmechanicalswitchbounceswillalsohavenoeffect.TheSRflip-flopcanthenbeRESETautomaticallyafterashortperiodoftime,forexample0.5seconds,soastoregisteranyadditionalandintentionalrepeatinputsfromthesameswitchcontacts,suchasmultipleinputsfromakeyboards“RETURN”key. CommonlyavailableIC’sspecificallymadetoovercometheproblemofswitchbouncearetheMAX6816,singleinput,MAX6817,dualinputandtheMAX6818octalinputswitchdebouncerIC’s.Thesechipscontainthenecessaryflip-flopcircuitrytoprovidecleaninterfacingofmechanicalswitchestodigitalsystems. Set-ResetbistablelatchescanalsobeusedasMonostable(one-shot)pulsegeneratorstogenerateasingleoutputpulse,eitherhighorlow,ofsomespecifiedwidthortimeperiodfortimingorcontrolpurposes.The74LS279isaQuadSRBistableLatchIC,whichcontainsfourindividualNANDtypebistable’swithinasinglechipenablingswitchdebounceormonostable/astableclockcircuitstobeeasilyconstructed. QuadSRBistableLatch74LS279 GatedorClockedSRFlip-Flop ItissometimesdesirableinsequentiallogiccircuitstohaveabistableSRflip-flopthatonlychangesstatewhencertainconditionsaremetregardlessoftheconditionofeithertheSetortheResetinputs. Byconnectinga2-inputANDgateinserieswitheachinputterminaloftheSRFlip-flopaGatedSRFlip-flopcanbecreated.Thisextraconditionalinputiscalledan“Enable”inputandisgiventheprefixof“EN“.TheadditionofthisinputmeansthattheoutputatQonlychangesstatewhenitisHIGHandcanthereforebeusedasaclock(CLK)inputmakingitlevel-sensitiveasshownbelow. GatedSRFlip-flop WhentheEnableinput“EN”isatlogiclevel“0”,theoutputsofthetwoANDgatesarealsoatlogiclevel“0”,(ANDGateprinciples)regardlessoftheconditionofthetwoinputsSandR,latchingthetwooutputsQandQintotheirlastknownstate. Whentheenableinput“EN”changestologiclevel“1”thecircuitrespondsasanormalSRbistableflip-flopwiththetwoANDgatesbecomingtransparenttotheSetandResetsignals. Thisadditionalenableinputcanalsobeconnectedtoaclocktimingsignal(CLK)addingclocksynchronisationtotheflip-flopcreatingwhatissometimescalleda“ClockedSRFlip-flop“. SoaGatedBistableSRFlip-flopoperatesasastandardbistablelatchbuttheoutputsareonlyactivatedwhenalogic“1”isappliedtoitsENinputanddeactivatedbyalogic“0”. InthenexttutorialaboutSequentialLogicCircuits,wewilllookatanothertypeofsimpleedge-triggeredflip-flopwhichisverysimilartotheRSflip-flopcalledaJKFlip-flopnamedafteritsinventor,JackKilby.TheJKflip-flopisthemostwidelyusedofalltheflip-flopdesignsasitisconsideredtobeauniversaldevice. NextTheJKFlipFlop ReadmoreTutorialsinSequentialLogic 1.SequentialLogicCircuits 2.TheJKFlipFlop 3.Multivibrators 4.TheD-typeFlipFlop 5.TheShiftRegister 6.JohnsonRingCounter 7.ConversionofFlip-flops 8.TheToggleFlip-flop 187Comments JointheconversationCancelreplyError!Pleasefillallfields. Notifymeoffollow-upcommentsbyemail. Δ GauravPandey Soverybasicfrom PostedonMay26th2022|1:26pm Reply Kurdapya ExplainTheStateofAsequentialCircuit Astatevariableinasequentialcircuitrepresentsthe single-bitvariableQstoredinamemoryelementin circuit. – Eachmemoryelementmaybeinstate0orstate1dependingon thecurrentvaluestoredinthememoryelement. TheStateofAsequentialCircuit: – Thecollectionofallstatevariables(memoryelementstored values)thatatanytimecontainalltheinformationaboutthe pastnecessarytoaccountforthecircuit’sfuturebehavior. – Asequentialcircuitthatcontainsnmemoryelementscouldbe inoneofamaximumof2nstatesatanygiventimedepending onthestoredvaluesinthememoryelements. – SequentialCircuitStatetransition:Achangeinthestored valuesinmemoryelementsthuschangingthesequentialcircuit fromonestatetoanother. PostedonMay18th2022|2:44pm Reply KhanyisoMathe Thisissopowerful.WhichsequencingisusedinenginecontrolunitC.P.U. PostedonApril17th2022|2:33pm Reply Ruth WhichlogicgatedoyouaddtoconvertanS-RlatchtoanS-RlatchwithEnable? PostedonMarch29th2022|8:25am Reply WayneStorr PleasereadtheGatedSRflip-floppartofthetutorial PostedonMarch29th2022|10:11am Reply Mark Whyaretheoutputsstatedtobeinverse? Iseenoreasonthattheinputs0and0couldnotgenerateoutputsof1and1apartfromtheassertionthattheoutputsareinverse.Nooneseemstoexplainwhytheseoutputscannotbeidentical. PostedonMarch02nd2022|3:59am Reply WayneStorr BecausethenitwouldnotbeaBistableLatch,justanotherlogiccircuit.Youcouldaddaninverter(NOTGate)ontooneoftheoutputstoachieve0-0or1-1.Butwhat’sthepoint. PostedonMarch02nd2022|7:47am Reply AnneMarie DifferentbetweenJKflipflopandSRflipflop PostedonJanuary28th2022|7:23am Reply WayneStorr PleasereadthetutorialsaboutJKandSRflip-flops PostedonJanuary28th2022|7:29am Reply DhruvaNS wondrfull PostedonJanuary24th2022|6:47am Reply MUHAMMADALI InthecircuitofFigure1,inputsA,B,andCareallinitiallyLOW.OutputYissupposedtogoHIGHonlywhenA,B,andCgoHIGHinacertainsequence.Analyzethecircuitto (a)DeterminethesequencethatwillmakeYgoHIGH. (b)ExplainwhytheSTARTpulseisneeded. (c)ModifythiscircuittouseDFFs. PostedonJanuary17th2022|8:55pm Reply Denismvanda Understandable PostedonDecember22nd2021|12:11pm Reply SteveWyatt HowcanImakeashiftregisterthatshiftsleftbuteachoutputstaysonaftershiftuntilalloutputsareon?Need16points.IthinkIneedalatchforeachoutput,4shiftregisterchipsalsocanthesftdriveLEDsdirectorIneedatransistor? PostedonDecember07th2021|3:20am Reply oleksiishevtsov FirsttruthtableyougothasQ′thatmergeswiththebackgroundcolor. PostedonSeptember07th2021|8:40pm Reply WayneStorr Thanks🙂 PostedonSeptember08th2021|9:45am Reply TAVONGAMARE Thisvideoprovidedagreatsupporthenceitismuchappreciatedinrelationtothestudiescarriedoutsofar,Ithereforeencourageyoutokeeponmaintainingsuchagoodcharacterinresearchingandprovidingsuchapowerofstudy.TheresearchcarriedsofarseemstoholdmorewaterthatwheneveriwanttoattendalectureitwillbefarmuchbetterformetounderstandwhoisthebestofallbetweenthegooglescholarandothersocialmediaplatformssuchaswhatsAppandfacebook.AddingmoreonthatiasloencouragedyoutokeepondoingthegreatworkseenfromtheUniversityofZimbabweundertheleaderslhipofChangamiredombohereundertheconstructionoftheGreatUniversityundertheleadershipofEngineerDRCharless PostedonJune30th2021|7:35pm Reply Veryinterested Ilovedthis PostedonMarch13th2021|10:03am Reply Koushikpal Howmanytypeoftruthtableins-rflip-flop? PostedonMarch08th2021|8:11pm Reply alpha IsthereamistakeinTheNORGateSRFlip-floptable?whenSis1andRis0,doesn’ttheoutputQshouldbe1? PostedonFebruary19th2021|3:53pm Reply WayneStorr No,thetutorialiscorrectasgiven. PostedonFebruary19th2021|4:57pm Reply Alpha Butwhen,wegivethesetinputas1,whytheoutputQisnot1?I’mbitconfused.Ithoughtsettingmeans,settingtheoutputto1 PostedonFebruary19th2021|5:01pm Reply ARITRASINGHACHOWDHURY Hello, Canyoupls.explainpresetandclearfunctionofflipflopwiththehelpoftransistor?Blockdias.arenothelpful.Itwillbeeasiertounderstand. Thanks PostedonFebruary18th2021|4:29am Reply WayneStorr Forflip-flops,thePRESET(PRE)inputisbasicallythesameasSET,thatisSetorPresetputstheoutputatQintoaHIGH(logic1)state.TheCLEAR(CLR)inputisthesameasRESET,inthatitClearsorResetstheoutputatQtoaLOW(logic0)state.Preset–toSet,andClear–toReset,canbeusedtoswitchtheflip-flopintoaknownorwantedinitialstate,withoutputQeitherHIGHorLOW. PostedonFebruary18th2021|3:59pm Reply Sakaria A flipflop isanelectroniccircuitwithtwostablestatesthatcanbeusedtostorebinarydata.Thestoreddatacanbechangedbyapplyingvaryinginputs. Flip-flops andlatchesarefundamentalbuildingblocksofdigitalelectronicssystemsusedincomputers,communications,andmanyothertypesofsystems. PostedonFebruary18th2021|7:49am Reply CharlFrancoisMarais Goodday. Justaquestion,aboutthepositivenorgateRS-latch. *Throughouttheexplanationitisstatedthat –whenacircuitissetthelogiclevelatQ=1 –whenacircuitisresetthelogiclevelatQ=0 –whythenaretheQlogiclevelsforsetandresetreversedforthetruthtableofthepositiveRS-latch? *WhenIswoptheinputsforthepositiveRS-latcharound,puttingRasthetopinputandSatthebottominputandIrunthelogicstocompletethetruthtable,IdoobtainresultsweresetwillresultinQ=1andresetwillresultinQ=0.AmIcorrectinthisassumption? InamateacherinSouthAfricateachingdigitalelectronicsforgr10to12learners.Thankyouverymuchforyoursite,ithelpsmylearnersverymuchasareverencematerialfortherearelotsofmistakesintheirtextbook. Regards C.F.Marais PostedonDecember26th2020|8:38am Reply zamanhameed GoodAppericiateit. PostedonNovember19th2020|9:25am Reply KenMeacham Iwouldlikeaverysimplecircuitthatwhentheinputispulsedlowtheoutputgoeslowandstayslowthenwhenthesameinputispulsedlowagaintheoutputreturnstothepreviousstateorahighstate. PostedonNovember13th2020|7:01pm Reply WayneStorr JKflip-flopconfiguredtotoggle,thatisJ=K=1 PostedonNovember13th2020|7:15pm Reply shambhuling super PostedonSeptember22nd2020|9:19am Reply ViewMore ReadmoreTutorialsinSequentialLogic 1.SequentialLogicCircuits 2.TheJKFlipFlop 3.Multivibrators 4.TheD-typeFlipFlop 5.TheShiftRegister 6.JohnsonRingCounter 7.ConversionofFlip-flops 8.TheToggleFlip-flop LookingforDataSheets? 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