D-type Flip Flop Counter or Delay Flip-flop - Electronics Tutorials

The D flip-flop is an edge triggered device which transfers input data to Q on clock rising or falling edge. Data Latches are level sensitive devices such as ... X Registertodownloadpremiumcontent! Registertodownloadpremiumcontent! X Deutsch Polski Register LogIn ACCircuits Amplifiers Attenuators BinaryNumbers BooleanAlgebra Capacitors CombinationalLogic Connectivity Counters DCCircuits Diodes Electromagnetism Filters Inductors Input/OutputDevices LogicGates MiscellaneousCircuits OperationalAmplifiers Oscillator PowerElectronics PowerSupplies Premium RCNetworks Resistors Resources SequentialLogic Systems Transformers Transistors Uncategorized WaveformGenerators PremiumContent FurtherEducation Sitemap ContactUs Home / SequentialLogic / TheD-typeFlipFlop TheD-typeFlipFlop TheD-typeflip-flopisamodifiedSet-Resetflip-flopwiththeadditionofaninvertertopreventtheSandRinputsfrombeingatthesamelogiclevel OneofthemaindisadvantagesofthebasicSRNANDGateBistablecircuitisthattheindeterminateinputconditionofSET=“0”andRESET=“0”isforbidden. Thisstatewillforcebothoutputstobeatlogic“1”,over-ridingthefeedbacklatchingactionandwhicheverinputgoestologiclevel“1”firstwilllosecontrol,whiletheotherinputstillatlogic“0”controlstheresultingstateofthelatch. Butinordertopreventthisfromhappeninganinvertercanbeconnectedbetweenthe“SET”andthe“RESET”inputstoproduceanothertypeofflipflopcircuitknownasaDataLatch,Delayflipflop,D-typeBistable,D-typeFlipFloporjustsimplyaDFlipFlopasitismoregenerallycalled. TheDFlipFlopisbyfarthemostimportantofalltheclockedflip-flops.Byaddinganinverter(NOTgate)betweentheSetandResetinputs,theSandRinputsbecomecomplementsofeachotherensuringthatthetwoinputsSandRareneverequal(0or1)toeachotheratthesametimeallowingustocontrolthetoggleactionoftheflip-flopusingonesingleD(Data)input. ThenthisDatainput,labelled“D”andisusedinplaceofthe“Set”signal,andtheinverterisusedtogeneratethecomplementary“Reset”inputtherebymakingalevel-sensitiveD-typeflip-flopfromalevel-sensitiveSR-latchasnowS=DandR=notDasshown. D-typeFlip-FlopCircuit   WerememberthatasimpleSRflip-floprequirestwoinputs,oneto“SET”theoutputandoneto“RESET”theoutput.Byconnectinganinverter(NOTgate)totheSRflip-flopwecan“SET”and“RESET”theflip-flopusingjustoneinputasnowthetwoinputsignalsarecomplementsofeachother.ThiscomplementavoidstheambiguityinherentintheSRlatchwhenbothinputsareLOW,sincethatstateisnolongerpossible. Thusthissingleinputiscalledthe“DATA”input.IfthisdatainputisheldHIGHtheflipflopwouldbe“SET”andwhenitisLOWtheflipflopwouldchangeandbecome“RESET”.However,thiswouldberatherpointlesssincetheoutputoftheflipflopwouldalwayschangeoneverypulseappliedtothisdatainput. Toavoidthisanadditionalinputcalledthe“CLOCK”or“ENABLE”inputisusedtoisolatethedatainputfromtheflipflop’slatchingcircuitryafterthedesireddatahasbeenstored.TheeffectisthatDinputconditionisonlycopiedtotheoutputQwhentheclockinputisactive.ThisthenformsthebasisofanothersequentialdevicecalledaDFlipFlop. The“Dflipflop”willstoreandoutputwhateverlogiclevelisappliedtoitsdataterminalsolongastheclockinputisHIGH.OncetheclockinputgoesLOWthe“set”and“reset”inputsoftheflip-floparebothheldatlogiclevel“1”soitwillnotchangestateandstorewhateverdatawaspresentonitsoutputbeforetheclocktransitionoccurred.Inotherwordstheoutputis“latched”ateitherlogic“0”orlogic“1”. TruthTablefortheD-typeFlipFlop Clk D Q Q Description ↓»0 X Q Q Memory nochange ↑»1 0 0 1 ResetQ»0 ↑»1 1 1 0 SetQ»1 Notethat:↓and↑indicatesdirectionofclockpulseasitisassumedD-typeflipflopsareedgetriggered TheMaster-SlaveDFlipFlop ThebasicD-typeflipflopcanbeimprovedfurtherbyaddingasecondSRflip-floptoitsoutputthatisactivatedonthecomplementaryclocksignaltoproducea“Master-SlaveD-typeflipflop”.Ontheleadingedgeoftheclocksignal(LOW-to-HIGH)thefirststage,the“master”latchestheinputconditionatD,whiletheoutputstageisdeactivated. Onthetrailingedgeoftheclocksignal(HIGH-to-LOW)thesecond“slave”stageisnowactivated,latchingontotheoutputfromthefirstmastercircuit.Thentheoutputstageappearstobetriggeredonthenegativeedgeoftheclockpulse.“Master-SlaveD-typeflipflops”canbeconstructedbythecascadingtogetheroftwolatcheswithoppositeclockphasesasshown. TheMaster-SlaveDFlipFlopCircuit   Wecanseefromabovethatontheleadingedgeoftheclockpulsethemasterflip-flopwillbeloadingdatafromthedataDinput,thereforethemasteris“ON”.Withthetrailingedgeoftheclockpulsetheslaveflip-flopisloadingdata,i.e.theslaveis“ON”.Thentherewillalwaysbeoneflip-flop“ON”andtheother“OFF”butneverboththemasterandslave“ON”atthesametime.Therefore,theoutputQacquiresthevalueofD,onlywhenonecompletepulse,ie,0-1-0isappliedtotheclockinput. TherearemanydifferentDflip-flopIC’savailableinbothTTLandCMOSpackageswiththemorecommonbeingthe74LS74whichisaDualDflip-flopIC,whichcontainstwoindividualDtypebistable’swithinasinglechipenablingsingleormaster-slavetoggleflip-flopstobemade.OtherDflip-flopIC’sincludethe74LS174HEXDflip-flopwithdirectclearinput,the74LS175QuadDflip-flopwithcomplementaryoutputsandthe74LS273OctalD-typeflipflopcontainingeightD-typeflipflopswithaclearinputinonesinglepackage. 74LS74DualD-typeFlipFlop OtherPopularD-typeflip-flopICs DeviceNumber Subfamily DeviceDescription 74LS74 LSTTL DualD-typeFlipFlopswithPresetandClear 74LS175 LSTTL QuadD-typeFlipFlopswithClear 74LS273 LSTTL OctalD-typeFlipFlopswithClear 4013B StandardCMOS DualtypeDFlipFlop 40174B StandardCMOS HexD-typeFlipFlopwithMasterReset UsingTheD-typeFlipFlopForFrequencyDivision OnemainuseofaD-typeflipflopisasaFrequencyDivider.IftheQoutputonaD-typeflip-flopisconnecteddirectlytotheDinputgivingthedeviceclosedloop“feedback”,successiveclockpulseswillmakethebistable“toggle”onceeverytwoclockcycles. InthecounterstutorialswesawhowtheDataLatchcanbeusedasa“BinaryDivider”,ora“FrequencyDivider”toproducea“divide-by-2”countercircuit,thatis,theoutputhashalfthefrequencyoftheclockpulses.ByplacingafeedbacklooparoundtheD-typeflipflopanothertypeofflip-flopcircuitcanbeconstructedcalledaT-typeflip-flopormorecommonlyaT-typebistable,thatcanbeusedasadivide-by-twocircuitinbinarycountersasshownbelow. Divide-by-2Counter   Itcanbeseenfromthefrequencywaveformsabove,thatby“feedingback”theoutputfromQtotheinputterminalD,theoutputpulsesatQhaveafrequencythatareexactlyonehalf( ƒ/2 )thatoftheinputclockfrequency,( ƒIN ).Inotherwordsthecircuitproducesfrequencydivisionasitnowdividestheinputfrequencybyafactoroftwo(anoctave)asQ=1onceeverytwoclockcycles. DFlipFlopsasDataLatches Aswellasfrequencydivision,anotherusefulapplicationoftheDflipflopisasaDataLatch.Adatalatchcanbeusedasadevicetoholdorrememberthedatapresentonitsdatainput,therebyactingabitlikeasinglebitmemorydeviceandIC’ssuchastheTTL74LS74ortheCMOS4042areavailableinQuadformatexactlyforthispurpose.Byconnectingtogetherfour,1-bitdatalatchessothatalltheirclockinputsareconnectedtogetherandare“clocked”atthesametime,asimple“4-bit”Datalatchcanbemadeasshownbelow. 4-bitDataLatch TransparentDataLatch TheDataLatchisaveryusefuldeviceinelectronicandcomputercircuits.TheycanbedesignedtohaveveryhighoutputimpedanceatbothoutputsQanditsinverseorcomplementoutputQtoreducetheimpedanceeffectontheconnectingcircuitwhenusedasabuffer,I/Oport,bi-directionalbusdriverorevenadisplaydriver. Butasingle“1-bit”datalatchisnotverypracticaltouseonitsownandinsteadcommerciallyavailableIC’sincorporate4,8,10,16oreven32individualdatalatchesintoonesingleICpackage,andonesuchICdeviceisthe74LS373OctalD-typetransparentlatch. Theeightindividualdatalatchesorbistablesofthe74LS373are“transparent”D-typeflip-flops,meaningthatwhentheclock(CLK)inputisHIGHatlogiclevel“1”,(butcanalsobeactivelow)theoutputsatQfollowsthedataDinputs. Inthisconfigurationthelatchissaidtobe“open”andthepathfromDinputtoQoutputappearstobe“transparent”asthedataflowsthroughitunimpeded,hencethenametransparentlatch. WhentheclocksignalisLOWatlogiclevel“0”,thelatch“closes”andtheoutputatQislatchedatthelastvalueofthedatathatwaspresentbeforetheclocksignalchangedandnolongerchangesinresponsetoD. 8-bitDataLatch Functionaldiagramofthe74LS373OctalTransparentLatch TheD-typeFlipFlopSummary ThedataorD-typeFlipFlopcanbebuiltusingapairofback-to-backSRlatchesandconnectinganinverter(NOTGate)betweentheSandtheRinputstoallowforasingleD(data)input.ThebasicDflipflopcircuitcanbeimprovedfurtherbyaddingasecondSRflip-floptoitsoutputthatisactivatedonthecomplementaryclocksignaltoproducea“Master-SlaveDflip-flop”device. ThedifferencebetweenaD-typelatchandaD-typeflip-flopisthatalatchdoesnothaveaclocksignaltochangestatewhereasaflip-flopalwaysdoes.TheDflip-flopisanedgetriggereddevicewhichtransfersinputdatatoQonclockrisingorfallingedge.DataLatchesarelevelsensitivedevicessuchasthedatalatchandthetransparentlatch. InthenexttutorialaboutSequentialLogicCircuits,wewilllookatconnectingtogetherdatalatchestoproduceanothertypeofsequentiallogiccircuitcalledaShiftRegisterthatareusedtoconvertparalleldataintoserialdataandviceversa. PreviousMultivibrators NextTheShiftRegister ReadmoreTutorialsinSequentialLogic 1.SequentialLogicCircuits 2.TheJKFlipFlop 3.Multivibrators 4.TheD-typeFlipFlop 5.TheShiftRegister 6.JohnsonRingCounter 7.ConversionofFlip-flops 8.TheToggleFlip-flop 45Comments JointheconversationCancelreplyError!Pleasefillallfields. Notifymeoffollow-upcommentsbyemail. Δ Azam HowcantheMasterSlavebemadetotriggeronthepositiveedgeinsteadofthenegative? PostedonApril16th2021|4:53pm Reply Maweni Quiteinformativepleasekeepthegoodwork PostedonDecember22nd2020|12:50pm Reply MohamadAlsayyed Verynicewaytogetinformation….. Thanksforwhodidandhelp..tocreateallthis.. Againthx PostedonAugust06th2020|11:05am Reply Shubhamgaikwad Good PostedonDecember06th2019|6:23am Reply Shubhamgaikwad Thanku Forgivingmeallcorrectandprperdetails Soualsoreferit,veryuseful PostedonDecember06th2019|6:22am Reply nishkarshahuja itssogoodandeasytounderstandthnksforfullfillourneeds. PostedonNovember18th2019|6:01pm Reply BasseyCelestineBassey PlsIneededmoreexplanationswiththis PostedonMarch09th2020|1:07pm Reply Hatiharan Ilikesubject PostedonSeptember08th2019|3:30pm Reply saipraneeth Thisisveryusefultolearnthetopicintheverylesstime.icanjustreferthisbloginsteadofreferringtowholeofmyreferencebookbeforegoingtomyexam PostedonNovember12th2018|3:43pm Reply Rehan Theirshouldbeproperdetailsofaskedquestions PostedonOctober18th2018|9:12am Reply PavanNayani Notsureifthisistheplacetoaskforhelpbutheregoes–usinga74ls74dualflip-flopchipinthehopeofreducingspeedopulsesbyhalf–usedthisinfoandmadeupthecircuitwithfeedbackloop–doublecheckedbutwillnotdivideby2–speedoreadsthesamewithorwithoutthecircuitintheloop–whatamImissing? PostedonJune11th2018|1:23pm Reply WayneStorr Forthe74ls74dualD-typeflip-floptotoggle,pin-1,pin-4andpin-14toVcc,pin-7to0v,pin-6connecteddirectlytopin-2. Apositivegoingpulseappliedtopin-3willcausepin-5(Q)tochangestateeverysecondpulseonpin-3 Repeatforthesecondflip-flopwithinthe74ls74 PostedonJune11th2018|3:19pm Reply WilliamScannell Liketotouchbasewithsomeonethatwouldbegood….cheers PostedonJune09th2018|1:45pm Reply MURASOLI Cansentmeshiftregisteroperationtable. ForD-flipflopshiftregister PostedonMarch20th2018|3:00pm Reply Bengusmandar Howtochangeandconvertsignaltodriverontransmitersystem? PostedonMarch08th2018|4:32am Reply KhinMohMohTin Țhankyouforthistuțorials PostedonJanuary20th2018|10:14pm Reply AnandthanMirzathanLoganathan Yaboisnerds PostedonNovember29th2017|1:23pm Reply Bhuvanesh ListtheIC’Susedforflipflops.Shiftregister,counterwiththerepindiagram. PostedonOctober15th2017|5:06am Reply Neil Notsureifthisistheplacetoaskforhelpbutheregoes–usinga74ls74dualflip-flopchipinthehopeofreducingspeedopulsesbyhalf–usedthisinfoandmadeupthecircuitwithfeedbackloop–doublecheckedbutwillnotdivideby2–speedoreadsthesamewithorwithoutthecircuitintheloop–whatamImissing? PostedonOctober06th2017|7:04pm Reply WayneStorr The74LS74isadualpositive-edgetriggeredD-typeflip-flopwhichcanbeconfiguredtoperformasadivide-by-twocounter.Buttodoso,!PRand!CLRmustbetiedtogetherHIGH(tologic-1),NOT-QconnectedtoD(feedbackloop)andtheclocksignalapplieddirectlytoCLK.TheoutputispresentonQ. PostedonOctober08th2017|8:10am Reply ANTONIO veryusefulinformation,thankyousomuch PostedonAugust27th2017|5:46am Reply snehnayak right PostedonAugust20th2017|10:14am Reply DrLaiLaiKhaing Perfectnotesthankuπ PostedonJuly08th2017|9:53am Reply ViewMore ReadmoreTutorialsinSequentialLogic 1.SequentialLogicCircuits 2.TheJKFlipFlop 3.Multivibrators 4.TheD-typeFlipFlop 5.TheShiftRegister 6.JohnsonRingCounter 7.ConversionofFlip-flops 8.TheToggleFlip-flop LookingforDataSheets? Close TheBasics ContactUs PrivacyPolicy TermsofUse ForAdvertisers ContactSales MediaGuideRequest AspencoreNetwork EDN EETimes EEWeb ElectronicProducts PowerElectronicsNews EPSNews Embedded PlanetAnalog ElectroSchematics TechOnline Datasheets.com ElectronicsKnowHow IoTTimes GlobalNetwork EETimesAsia EETimesChina EETimesIndia EETimesJapan EETimesTaiwan EDNAsia EDNChina EDNTaiwan EDNJapan ESMChina ConnectwithUs Facebook AllcontentsareCopyright©2022byAspenCore,Inc.Allrightsreserved. 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