NAND-gate| Digital Logic Gates - Electronics-Tutorial.net

The Boolean expression for three input NAND gate and The truth table of the three input NAND gate is also shown in figure. Four input AND gate. Four input AND ... MiniProjects MATLABProjects VLSIProjects ArduinoProjects ProjectIdeas More ✕ electronicsTutorials MiniProjects MATLABProjectss VLSIProjects ArduinoProjects electronicsProjects ProjectIdeas Quiz Home>digitallogicgates>nandgate Prev Next NANDGate NANDstandsforNOTAND.AnANDgatefollowedbyaNOTcircuitmakesita NANDgateFigureshowsthecircuitsymbolofatwo-inputNANDgate.The truthtableofaNANDgateisobtainedfromthetruthtableofanANDgate bycomplementingtheoutputentries.TheoutputofaNANDgateisalogic0 whenallitsinputsarealogic1.Forallotherinputcombinations,the outputisalogic1.NANDgateoperationislogicallyexpressedasY= CMOSNANDGate Thecircuitbelowhastwoinputsandoneoutput.Wheneveratleastoneof theinputsislow,thecorrespondingPMOStransistorwillbeconducting whiletheNMOStransistorwillbeclosed.Consequently,theoutputvoltage willbehigh.Conversely,ifbothinputsarehigh,thenbothPMOS transistorsatthetopwillbeopencircuitsandbothNMOStransistorswill beconducting.Hence,theoutputvoltageislow.Thefunctionofthisgate canbesummarizedbythetable.Iflogical1'sareassociatedwithhigh voltagesthenthefunctionofthisgateiscalledNANDfornegatedAND.Again,thereisneveraconductingpathfromthe supplyvoltagetoground. TTLNANDGate CircuitbelowshowstheTTLimplementationofNANDgate.Here,R1andR2 arethepull-upresistors.VCCisthepowersupply.T1isthebipolar junctiontransistoroperatedintotempoleconfiguration.T2isthenormal transistor. ThreeinputNANDgate FigureaboveshowsthethreeinputANDgate.Inthisfigure, 1)WhentheinputsA=0,B=0andC=0thentheoutputY=1 2)WhentheinputsA=0,B=0andC=1thentheoutputY=1 3)WhentheinputsA=0,B=1andC=0thentheoutputY=1 4)WhentheinputsA=0,B=1andC=1thentheoutputY=1 5)WhentheinputsA=1,B=0andC=0thentheoutputY=1 6)WhentheinputsA=1,B=0andC=1thentheoutputY=1 7)WhentheinputsA=1,B=1andC=0thentheoutputY=1 8)WhentheinputsA=1,B=1andC=1thentheoutputY=0 TheBooleanexpressionforthreeinputNANDgateandThetruthtableofthe threeinputNANDgateisalsoshowninfigure. FourinputANDgate FigureaboveshowsthefourinputANDgate.Inthisfigure, 1)WhentheinputsA=0,B=0,C=0andD=0thentheoutputY=1 2)WhentheinputsA=0,B=0,C=0andD=1thentheoutputY=1 3)WhentheinputsA=0,B=0,C=1andD=0thentheoutputY=1 4)WhentheinputsA=0,B=0,C=1andD=1thentheoutputY=1 5)WhentheinputsA=0,B=1,C=0andD=0thentheoutputY=1 6)WhentheinputsA=0,B=1,C=0andD=1thentheoutputY=1 7)WhentheinputsA=0,B=1,C=1andD=0thentheoutputY=1 8)WhentheinputsA=0,B=1,C=1andD=1thentheoutputY=1 9)WhentheinputsA=1,B=0,C=0andD=0thentheoutputY=1 10)WhentheinputsA=1,B=0,C=0andD=1thentheoutputY=1 11)WhentheinputsA=1,B=0,C=1andD=0thentheoutputY=1 12)WhentheinputsA=1,B=0,C=1andD=1thentheoutputY=1 13)WhentheinputsA=1,B=1,C=0andD=0thentheoutputY=1 14)WhentheinputsA=1,B=1,C=0andD=1thentheoutputY=1 15)WhentheinputsA=1,B=1,C=1andD=0thentheoutputY=1 16)WhentheinputsA=1,B=1,C=1andD=1thentheoutputY=0 TheBooleanexpressionforfourinputNANDgateandthetruthtableofthe fourinputNANDgateisalsoshowninfigure. FormthisanalysisofANDgatewecanseethat, 1)Foratwo-inputNANDgate,Output=(A.B)' 2)Forathree-inputNANDgate,Output=(A.B.C)' 3)Forafour-inputNANDgate,Output=(A.B.C.D)' NANDgateasaUniversalgate TheNANDisalsoknownasuniversalgate.BecausebyusingonlyNANDgate anykindofBooleanlogicgatecanbeimplemented.ByusingNANDgatewe caneasilyimplementtheANDgate,ORgateandtheNOTgate. ImplementationofNOTgateusingNANDgate. FigurebelowshowstheimplementationoftheNOTgateusingNANDgate.By shortingthetwoinputsoftheNANDgatetogethertheNOTgatecanbe implemented. ImplementationofANDgateusingNANDgate. FigurebelowshowstheimplementationoftheANDgateusingNANDgate. Here,byshortingthetwoinputsoftheNANDgatetogethertheNOTgatecan beimplemented.ThisimplementedNANDwhenwewillconnecttotheoutputof theNANDgatetheANDgatewillbeimplemented. ImplementationofORgateusingNANDgate. FigurebelowshowstheimplementationoftheORgateusingNANDgate.Here, byshortingthetwoinputsoftheNANDgatetogethertheNOTgatecanbe implemented.ThisimplementedNANDwhenwewillconnecttotheinputsof theNANDgatetheORgatewillbeimplemented. TTLNANDgateICs 1)7400Quad2-inputNANDgate 2)7410Triple3-inputNANDgate 3)7420Dual4-inputNANDgate 4)7430Single8-inputNANDgate CMOSNANDGateICs 1)4011Quad2-inputNANDgate 2)4023Triple3-inputNANDgate 3)4012Dual4-inputNANDgate Prev Next UsefulResources MiniProjects MATLABProjectss VLSIProjects ArduinoProjects Quiz x FaceBook AcdcpowerconverterssinglephasefullwavecontrolledrectifiersinglephasehalfwavecontrolledrectifierthreephasefullwavecontrolledrectifierthreephasehalfcontrolledrectifierAmplifierinstrumentationamplifierinvertingamplifierisolationamplifiernoninvertingamplifieroperationalamplifierunitygainbufferAnalogintegratedcircuitscurrenttovoltageconverterdataconverters*binaryweightedresistordac*countertypeadc*dualslopetypeadc*flashtypeadc*r2rladderdac*successiveapproximationtypeadcmultivibrators*asymmetricalsquarewavegenerator*bistablemultivibrators*monostablemultivibrator*sawtoothwaveformgenerator*triangularwaveformgeneratorocillatorsopampadderopampcomparators*comparatorasadutycyclecontroller*comparatorasafunctiongenerator*comparatoriclm311*invertingcomparator*noninvertingcomparator*voltagecontrolledoscillator*windowcomparatoropampdifferentiator*practicaldifferentiator*summingdifferentiatoropampintegrator*differenceintegral*noninvertingintegrator*practicalintegrator*summingintegratorpeakdetectorphaselockedloop*pllapplications*pllic565precisionrectifier*modifiedprecisionfullwaverectifier*nonsaturatedtypeprecisionhalfwaverectifier*precisionfullwaverectifier*saturatingtypeprecisionhwrsampleholdcircuitschmitttrigger*asymmetricalinvertingschmitttrigger*invertingschmitttrigger*noninvertingschmitttriggersubtractordifferenceamplifiervoltageregulator*adjustablenegativevoltageregulatorics*currentbooster*dualpowersupply*lowdropoutvoltageregulators*seriesregulatorusingopamp*threeterminaladjustablevoltageregulatorics*threeterminalfixedvoltageregulatorics*voltageregulatorsicsAnalogCMOSDesignCMOSDifferentialAmplifierCMRRCurrentMirrorsDifferentialAmplifierCascodeOpampFoldedCascodeOpampTwoStageOpampMOSFETAmplifiersCascodeAmplifierCMOSInverterasanAmplifierCommonDrainAmplifierCommonGateAmplifierCommonSourceAmplifierCSAmplifierwithActiveLoadCSAmplifierwithCurrentSourceLoadCurrentSourceLoadInverterFrequencyResponseofCSAmplifierPMOSLoadInverterPushPullInverterBodyEffectCurrentSinksCurrentSourceCVCharacteristicsEnhancementMOSFETPhysicalStructureIVCharacteristicsofPMOSTransistorLinearRegionofOperationMOSFETSmallSignalModelSaturationRegionofOperationThresholdVoltageMOSFETParasiticsInterconnectCapacitanceInterconnectDelayModelInterconnectResistanceParasiticcapacitanceModelsParasiticCapacitancesParasiticCapacitancesMOSFETSSourceDrainResistanceRFCMOSCircuitsLowNoiseAmplifierMixersOscillatorRFCircuitsADCCircuitsADCDACBlocksDACCircuitsSamplingAnalogSignalsSignalConditioningSignalQuantizationCombinationallogiccircuitsarithmeticlogicunitbinaryaddersubtractorbooleanalgebradecodersdemultiplexersencodersfulladderfullsubtractorhalfadderhalfsubtractormultiplexerControlsystemsfeedbackcontrolsystemtransferfunctionandcharacteristicequationtransferfunctionofelectricalcircuitDccircuitsenergysourceskirchhoffscurrentlawkirchhoffsvoltagelawmaximumpowertransfertheoremmeshanalysisnodalanalysisnortonstheoremsourcetransformationssuperpositiontheoremtheveninstheoremDcdcconverterchopperclassificationofchopperstepdownchopperstepupchopperswitchedmodepowersuppliessmpsuninterruptiblepowersupplyupsDctoacinverterhalfbridgedcacinvertersinglephasefullbridgeinvertersinglepwminvertersthreephaseinverterDigitalCMOSDesignCMOSInverterBetaRatioEffectsDissipationduetoDirectPathCurrentsDynamicPowerConsumptionNoiseMarginPowerDelayProductinCMOSPowerDissipationminimizationTechniquesStaticPowerConsumptionVTCCMOSInverterWidthLengthRatioCalculationofCMOSCMOSLayoutDesignCMOSDesignFlowCMOSlambdaDesignRulesDesignRuleCheckInverterLayoutLambdabaseddesignrulesLayoutDesignRulesLayoutoflogicgatesMicronDesignRulesStickDiagramsTechnologyscalingTypesofScalingCMOSLogicGatesCMOS4inputNORgateCMOSANDgateCMOSCompoundGatesCMOSHalfadderCMOSNANDGateCMOSNORGateCMOSORgateCMOSXNORandXORPullupandPullDownNetworksRulesforDesigningComplementaryCMOSGatesThreeinputCMOSNANDgateMOSCapacitorBandDiagramofIdealMOSBandDiagramofNonidealMOSBandDiagramofNonidealMOSwithBiasMOSDefinitionsMOSFETFundamentalsMOSFETFundamentalsIntroductionBasicMOSTransistorsMOSFETasSwitchnchannelDepletionModeMOSFETnchannelEnhancementModeMOSFETpchannelDepletionModeMOSFETpchannelEnhancementModeMOSFETNonIdealEffectsBodyEffectHotElectronEffectMobilityVariationSubthresholdConductionVelocitySaturationPassTransistorLogic21MUXusingtransmissiongate41multiplexerusingCMOSlogicORgateusingpasstransistorlogicTransmissionGateXNORgateusingpasstransistorlogicXORgateusingpasstransistorlogicPropagationDelayDelayEstimationElmoreDelayModelParasiticCapacitancesRCDelayModelofInverterRCDelayModelofNANDGateDigitallogicfamiliescmosandttlinterfacescmoslogicnoisemarginttllogicDigitallogicgatesandgatenandgatenorgatenotgateorgatexnorgatexorgateElectroniccomponentscapacitors*acanalysisofcapacitor*capacitivereactance*capacitorbasics*capacitorchargeequations*capacitortypes*capacitorsinparallelcombination*capacitorsinseriescombination*colourcodingincapacitors*multipleplatecapacitor*parallelplatecapacitorinductors*inductivereactance*inductorbasics*inductorsinparallelcombination*inductorsinseriescombination*mutualinductance*selfinductanceresistorstransformersElectronicdevicesdiodeinsulatedgatebipolartransistormosfetpowermosfettransistorsElectronicinstrumentsdigitalvoltmeters*dualslopedvm*ramptypedvmoscilloscope*cathoderayoscilloscopewaveformElectronicsystemsbrushlessdcmotorsinductionmotorpublicaddresssystemseparatelyexciteddcmotorservomotorssteppermotorFinitestatemachinesAlgorithmicStateMachines*ASMchart2bitupdowncounter*ASMchartforsignalgenerator*ASMcharts*ASMChartToolforSequentialCircuitDesign*DesignwithMultiplexersAsyncronousFSMDesign*AnalysisofAsynchronousSequentialMachines*AsynchronousFSM*DesignofAsynchronousSequentialMachine*DesignProcedureforAsynchronousSequentialCircuits*EssentialHazards*Hazardfreecircuit*ModesofAsynchronousSequentialMachinesFSMApplications*UARTTransmitterDesign*UARTReceiverDesign*TrafficLightController*SimpleTrafficController*SerialAdder*SequentialCountersJKFF*SequentialCountersDFF*SequentialCounters*SequenceGenerator*SequenceDetector*LiftControllerHazards*DetectionofStaticHazards*DynamicHazards*EffectsofHazards*EliminationofStaticHazards*StaticHazardsMetastability*JKflipflopStateMachine*Metastabilitymeasurementsetup*MetastabilitySynchronizerStateMachineFundamentals*AnalysisofSequentialCircuits*ExcitationTablesforFlipFlops*FiniteStateMachineDiagram*MealyFiniteStateMachine*MooreFiniteStateMachine*NeedforStateMachines*StateDiagrams*StateEncodingTechniques*StateMachine*StateMinimization*VHDLCodingofFSMNumbersystemsbinarynumbersystembinarynumbersbinarytodecimalconversiondecimalnumbersystemdecimaltobinaryconversiondecimaltohexadecimalconversiondecimaltooctalconversionhexadecimalnumbersystemhexadecimaltodecimalconversionoctalnumbersystemoctaltodecimalconversionProgrammableLogicDeviceArchitecturesCPLDAdvancedMicroDevicesAMDCPLDsAlteraFLASHlogicCPLDsAlteraMAX7000CPLDComplexProgrammableLogicDeviceCPLDsCPLDPackagingCypressFLASH370CPLDsICTPEELArraysLatticeCPLDsXC9500CPLDFamilyFPGAFieldprogrammablegatearrayFPGAFPGAProgrammingFPGAStructuresXC4000FPGAFamilyXC5200FPGAFamilyProgrammableLogicDevicesApplicationSpecificIntegratedCircuitsASICDiscreteDevicesTechnologyEvolutionofProgrammableLogicDevicesProgrammableArrayLogicPALProgrammableLogicArrayPLAProgrammableLogicDeviceTechnologyProgrammableReadonlyMemoryPROMSimpleProgrammableLogicDevicesSPLDProgrammablelogicdevicescomplexprogrammablelogicdevicefieldprogrammablegatearraygenericarraylogicprogrammablearraylogicprogrammablelogicarrayprogrammableromsSequentiallogiccircuitsasynchronouscountercountersdflipfloptojkflipflopdflipfloptosrflipflopdflipflopflipflopexcitationtablejkflipfloptodflipflopjkflipfloptosrflipflopconversionjkflipfloptotflipflopjkflipflopparallelintoparalleloutpiposhiftregisterparallelintoserialoutpisoshiftregisterserialintoparalleloutsiposhiftregisterserialintoserialoutsisoshiftregistershiftregisterssrflipfloptodflipflopsrflipfloptojkflipflopconversionsrflipflopsynchronouscountertoggleflipflopSystemOnChipClockDistributionClockJitterClockSkewInterconnectsInterconnectRoutingTechniquesRCWireModelWireCapacitanceWireResistanceWiringParasiticsPowerDistributionPowerDistributionTechniquesPowerOptimizationSignalIntegrityIssuesSupplyandGroundBounceSOCDesignsDesignValidationEMIImmuneDesignIOArchitecturesandPadDesignOffChipConnectionsOnePhaseSystemTwoPhaseSystemThyristorcharacteristicsofthyristorgatecharacteristicsofthyristorratingsofthyristorthyristorcommutationthyristorcommutationtechniquestriggeringcircuitofthyristorVHDL*HardwareDescriptionLanguages*IntroductiontoVHDL*VHDLProgramFormat*StructureofVHDLProgram*DataFlowModeling*Behavioralmodeling*Datatypes*Structuralmodeling*Mixedmodeling*DataObjectsandIdentifiers*HardwareDescriptionLanguages*Operators*Synthesis*TypesofDelays*VHDLProgramFormat*VHDLSimulation*VHDLstatements*Attributes*ConfigurationDeclaration*ConfigurationSpecification*Configurations*Function*Generics*Package*Procedure*Subprograms*TestBench*AdderSubtractor*ALU*Carryrippleadder*Comparators*Divider*Fulladder*Halfadder*Multiplier*nbitadder*SimpleEqualityComparator*Subtractor*Assertionstatement*BlockStatement*ComponentDeclarations*ComponentInstantiation*ConcurrentSignalAssignments*ExitStatements*ForgenerateStatement*GenerateStatements*Loopstatements*Nextstatements*ReportStatement*Returnstatements*WaitStatements*WhenStatement*withSelectStatementVlsiEvolutionofDigitalICTechnologiesICDevelopmentCycleVLSITechnologyVLSIDesignFlowCMOSICTechnology*BoundaryScanStandards*BoundaryScan*BuiltinLogicBlockObserverBILBO*BuiltinSelfTestingBIST*CombinationalLogicTesting*Controllability*FaultCoverage*FaultModeling*FullScan*ICTesting*JTAGTAPController*JTAG*LinearFeedbackShiftRegisterLFSR*NeedofDesignforTestability*Observability*PartialScan*ScanPathTesting*SignatureAnalysis*StuckopenandStuckshortFaults*Proj1ModulatorfordigitalterrestrialtelevisionaccordingtotheDTMBstandard*Proj2CANControllerDesign*Proj3RouterArchitectureforJunctionBasedSourceRouting*Proj4DesignSpaceExplorationOfFieldProgrammableCounter*Proj5MobileBroadbandReceiver*Proj6OBJECTTRACKINGALGORITHM*Proj7HardwareSoftwareRuntimeEnvironmentforReconfigurableComputers*Proj8FaceDetectionSystemUsingHaarClassifiers*Proj9FastHardwareDesignSpaceExploration*Proj10SpeedingUpFaultInjectionCampaignsonSafetyCriticalCircuits*Proj11HIGHSPEED4BITSFQMULTIPLIER*Proj12UniversalCryptographyProcessorforSmartCards*Proj13HIGHSPEEDMULTIPLIERUSINGSPURIOUSPOWERSUPPRESSION*Proj14LOSSLESSDATACOMPRESSIONHARDWAREARCHITECTURE*Proj15VLSIArchitectureForRemovalOfImpulseNoiseInImage*Proj16PROCESSORARCHITECTURESFORMULTIMEDIA*Proj17HighSpeedMultiplierAccumulatorUsingSPST*Proj18PowerEfficientLogicCircuitDesign*Proj19DataTransferforAMBABus*Proj20ATMKnockoutSwitchConcentrator*Proj21SynthesisofAsynchronousCircuits*Proj22AMBAAHBcompliantMemoryController*Proj23RippleCarryandCarrySkipAdders*Proj2432bitFloatingPointArithmeticUnit*Proj25CRCCircuitArchitecture*Proj26ONCHIPPERMUTATIONNETWORKFORMULTIPROCESSOR*Proj27VLSISystolicArrayMultiplierforsignalprocessingApplications*Proj28FloatingpointArithmeticLogicUnit*Proj29DDRSDRAMCONTROLLER*Proj30FFTProcessorUsingRadix4Algorithm*Proj31bitRISCProcessor*Proj32SMARTSENSOR*Proj33FuzzybasedPIDController*Proj34StepperMotorController*Proj35I2CBusController*Proj36SolarPowerSavingSystemforStreetLightsandAutomaticTrafficController*Proj37FuzzyBasedMobileRobotController*Proj38RealtimeTrafficLightControlSystem*Proj39DigitalSpaceVectorPWMThreePhaseVoltageSourceInverter*Proj40ComplexMultiplierUsingAdvanceAlgorithm*Proj41DiscreteWaveletTransform(DWT)forImageCompression*Proj42GaborFilterforFingerprintRecognition*Proj43FloatingPointFusedAddSubtractandmultiplierUnits*Proj44ORTHOGONALCODECONVOLUTIONCAPABILITIES*Proj45FlipFlopsforHighPerformanceVLSIApplications*Proj46LowPowerVideoCompressionAchitecture*Proj47PowerGatingImplementationwithBodyTiedTripleWellStructure*Proj48UNIVERSALASYNCHRONOUSRECEIVERTRANSMITTER*Proj49LOWPOWERMULTIPLIERUSINGCOMPOUNDCONSTANTDELAYLOGIC*Proj50FlashADCusingComparatorScheme*Proj51HighSpeedFloatingPointAdditionandSubtraction*Proj52LFSRbasedPseudorandomPatternGeneratorforMEMS*Proj53PowerOptimizationofLFSRforLowPowerBIST*Proj54VENDINGMACHINEUSINGVERILOG*Proj55VLSIARCHITECTURESFORDWT*Proj56CacheMemoryController*Proj57ChipForPrepaidElectricityBilling*Proj58HighSpeedNetworkDevicesUsingReconfigurableContentAddressableMemory*Proj59BitCarryLookAheadAdder*Proj60256bitParallelPrefixAdders*Proj61MutualAuthenticationProtocol*Proj62OverlapbasedLogiccell*Proj63LowPowerAdderCompressors*Proj64UTMIANDPROTOCOLLAYERFORUSB2.0*Proj655stagePipelinedArchitectureof8BitPicoProcessor*Proj66ControllerDesignforRemoteSensingSystems*Proj67TestPatternGenerationforBIST*Proj68FasterDaddaMultiplier*Proj69SINGLECYCLEACCESSSTRUCTUREFORLOGICTEST*Proj70LowDropOutVoltageRegulatorVlsidesignfortestabilityBoundaryScanStandardsBoundaryScanBuiltinLogicBlockObserverBILBOBuiltinSelfTestingBISTCombinationalLogicTestingControllabilityFaultCoverageFaultModelingFullScanICTestingJTAGTAPControllerJTAGLinearFeedbackShiftRegisterLFSRNeedofDesignforTestabilityObservabilityPartialScanScanPathTestingSignatureAnalysisStuckopenandStuckshortFaultsMiniprojects2BitParallelorFlashAnalogtoDigitalConverter3BitFlashTypeAnalogtoDigitalConverter3BITPARALLELtoSERIALDATACONVERTER41MULTIPLEXER4BitBinaryCounterAMPLITUDEMODULATIONANDDEMODULATIONAMPLITUDEMODULATIONANDDEMODULTIONUSINGBJTAMPLIFIERANDDIODEDETECTORANALOGSIGNALDIVIDERAnalogSignalsMultiplierANALOGTRNSMITTERANDRECEIVERASKModulationusingOPAMPAstatisticalcomparisonofbinaryweightedandR2R4BitDACAsynchronousDeviceforSerialDataTransmissionandReceptionforandroiddatatransmissionAsynchronousModulo16DownCounterAudioAmplifiercircuitwithnoisefilteringAUTOMATICRESISTANCEMETERFOR3PHASEINDUCTIONMOTORDESIGNANDSIMULATIONBistableMultivibratorusingAsymmetricalMosfetTriggeringCMOSBasedAnalogFunctionGeneratorCOMPANDERCOMPANDINGCIRCUITUSINGOPAMPSDCboostcircuitusing555timerDECADECOUNTERDecoderanditsAnalysisDesignandModellingofNotchFilterusingUniversalFilterFLTU2DesignandPhaseFrequencyDetectorUsingDifferentLogicGatesinCMOSProcessTechnologyDesignofAstableMultivibratorCircuitDESIGNOFOPAMPUSINGCMOSWITHIMPROVEDPARAMETERSDESIGNOFVARIABLEFREQUENCYDigitalThermometerusing1N4148DiodeDIGITALTOANALOGCONVERTERUSING8BITWEIGHTEDRESISTORSFMTRANSMITTERFourbitArithmeticLogicalUnitFREQUENCYSHIFTKEYINGUSING555FunctionGeneratorUsingOpAmpsGenerationofPWMusing555timerICHARTLEYANDCOLPITTSOSCILLATORUSINGOPAMPHeartBeatsensorusingPhotoplethysmographyIC555timerasanAudioAmplifierLOWCOSTMOSFETBASEDMOTORDRIVERMonostablemultivibratorMOSFETBASEDMOTORDRIVERMOSFETdrivercircuittointerfaceMOSFETswithmicrocontrollerforhighspeedapplicationPAMMODULATIONANDDEMODULATIONPhaseLockedLoopPIRMOTIONSENSORPULSEWIDTHMODULATIONPULSEWIDTHMODULATIONANDDEMODULATIONRegulatedDCPowerSupplyusingSeriesVoltageRegulatorSCHMITTTRIGGERUSING555SerialToParallelConvertorShortCircuitProtectedPowerSupplyShortRangeradioTransmitterandReceiverSIMULATIONOFFUNCTIONGENERATORSmallRangeDigitalThermometerusing1N4148ThreePhaseInverterusingMOSFETtodriveBLDCmotorandgeneralthreephaseLoadTHREESTAGEAMPLIFIERWITHCURRENTLIMITERTRANSISTORTESTERUSINGIC555TIMERTrulyrandomandPseudorandomDataGenerationwithThermalNoiseUNIVERSALACTIVEFILTERVOLTAGEREGULATORZenerDiodeTesterZENERDIODETESTERUSING555TIMERZeroCrossingDetectorVOLTAGEREGULATORZENERDIODETESTERUSING555TIMERZeroCrossingDetectorVlsiprojectsProj1ModulatorfordigitalterrestrialtelevisionaccordingtotheDTMBstandardProj2CANControllerDesignProj3RouterArchitectureforJunctionBasedSourceRoutingProj4DesignSpaceExplorationOfFieldProgrammableCounterProj5MobileBroadbandReceiverProj6OBJECTTRACKINGALGORITHMProj7HardwareSoftwareRuntimeEnvironmentforReconfigurableComputersProj8FaceDetectionSystemUsingHaarClassifiersProj9FastHardwareDesignSpaceExplorationProj10SpeedingUpFaultInjectionCampaignsonSafetyCriticalCircuitsProj11HIGHSPEED4BITSFQMULTIPLIERProj12UniversalCryptographyProcessorforSmartCardsProj13HIGHSPEEDMULTIPLIERUSINGSPURIOUSPOWERSUPPRESSIONProj14LOSSLESSDATACOMPRESSIONHARDWAREARCHITECTUREProj15VLSIArchitectureForRemovalOfImpulseNoiseInImageProj16PROCESSORARCHITECTURESFORMULTIMEDIAProj17HighSpeedMultiplierAccumulatorUsingSPSTProj18PowerEfficientLogicCircuitDesignProj19DataTransferforAMBABusProj20ATMKnockoutSwitchConcentratorProj21SynthesisofAsynchronousCircuitsProj22AMBAAHBcompliantMemoryControllerProj23RippleCarryandCarrySkipAddersProj2432bitFloatingPointArithmeticUnitProj25CRCCircuitArchitectureProj26ONCHIPPERMUTATIONNETWORKFORMULTIPROCESSORProj27VLSISystolicArrayMultiplierforsignalprocessingApplicationsProj28FloatingpointArithmeticLogicUnitProj29DDRSDRAMCONTROLLERProj30FFTProcessorUsingRadix4AlgorithmProj31bitRISCProcessorProj32SMARTSENSORProj33FuzzybasedPIDControllerProj34StepperMotorControllerProj35I2CBusControllerProj36SolarPowerSavingSystemforStreetLightsandAutomaticTrafficControllerProj37FuzzyBasedMobileRobotControllerProj38RealtimeTrafficLightControlSystemProj39DigitalSpaceVectorPWMThreePhaseVoltageSourceInverterProj40ComplexMultiplierUsingAdvanceAlgorithmProj41DiscreteWaveletTransform(DWT)forImageCompressionProj42GaborFilterforFingerprintRecognitionProj43FloatingPointFusedAddSubtractandmultiplierUnitsProj44ORTHOGONALCODECONVOLUTIONCAPABILITIESProj45FlipFlopsforHighPerformanceVLSIApplicationsProj46LowPowerVideoCompressionAchitectureProj47PowerGatingImplementationwithBodyTiedTripleWellStructureProj48UNIVERSALASYNCHRONOUSRECEIVERTRANSMITTERProj49LOWPOWERMULTIPLIERUSINGCOMPOUNDCONSTANTDELAYLOGICProj50FlashADCusingComparatorSchemeProj51HighSpeedFloatingPointAdditionandSubtractionProj52LFSRbasedPseudorandomPatternGeneratorforMEMSProj53PowerOptimizationofLFSRforLowPowerBISTProj54VENDINGMACHINEUSINGVERILOGProj55VLSIARCHITECTURESFORDWTProj56CacheMemoryControllerProj57ChipForPrepaidElectricityBillingProj58HighSpeedNetworkDevicesUsingReconfigurableContentAddressableMemoryProj59BitCarryLookAheadAdderProj60256bitParallelPrefixAddersProj61MutualAuthenticationProtocolProj62OverlapbasedLogiccellProj63LowPowerAdderCompressorsProj64UTMIANDPROTOCOLLAYERFORUSB2.0Proj655stagePipelinedArchitectureof8BitPicoProcessorProj66ControllerDesignforRemoteSensingSystemsProj67TestPatternGenerationforBISTProj68FasterDaddaMultiplierProj69SINGLECYCLEACCESSSTRUCTUREFORLOGICTESTProj70LowDropOutVoltageRegulatorMatlabprojectsProj1DESIGNOFFIRFILTERUSINGSYMMETRICSTRUCTUREProj2HybridMedianFilterdesignProj3DesigninganOptimalFuzzyLogicControllerofaDCMotorProj4BrainTumourExtractionfromMRIImagesProj5MammogramofBreastCancerdetectionProj6VEHICLENUMBERPLATERECOGNITIONUSINGMATLABProj7HighSpeedRailRoadTransportAutomationProj8ECONOMICANDEMISSIONDISPATCHUSINGALGORITHMSProj9DCDCConvertersforRenewableEnergySystemsProj10ADAPTIVEFILTERINGUSEDINHEARINGAIDSOFIMPAIREDPEOPLEProj11MODELINGOFTEMPERATUREPROCESSUSINGGENETICProj12CDMAMODEMDESIGNUSINGDIRECTSEQUENCESPREADSPECTRUM(DSSS)Proj13HydropowerPlantModelsProj14IEEE802.11BluetoothInterferenceSimulationstudyProj15InverseDataHidinginaClassicalImageProj16JPEGCOMPRESSORProj17DigitalImageArnoldTransformationandRC4AlgorithmsProj18HandGestureRecognitionProj19PerformanceStudyforHybridElectricVehiclesProj20WiFiAccessPointPlacementForIndoorLocalizationProj21NeuralNetworkBasedFaceRecognitionProj22TreeBasedTagCollisionResolutionAlgorithmsProj23BackPropagationNeuralNetworkforAutomaticSpeechRecognitionProj24OrthogonalFrequencyDivisionMultiplexing(OFDM)SignalingProj25SmartAntennaArrayUsingAdaptiveBeamformingProj26ImplementationofButterworthChebyshevIandEllipticFilterforSpeechAnalysisProj27SimulatorforAutonomousMobileRobotsProj28MethodtoExtractRoadsfromSatelliteImagesProj29RemoteDataAcquisitionUsingCdmaRfLinkProj30AUTOMATICTRAINOPERATIONANDCONTROLProj31DetectionofObjectsinCrowdedEnvironmentsProj32ArmatureControlledDirectCurrentProj33DistributionTransformerForProj34WAVELETTRANSFORMANDSTRANSFORMBASEDARTIFICIALNEURALProj35MULTISCALEEDGEBASEDTEXTEXTRACTIONProj36TransientStabilityAnalysisofPowerSystemProj37SinglephaseSPWMUnipolarinverterProj38InductionGeneratorforVariableSpeedWindEnergyConversionSystemsProj39ExtraHighVoltageLongTransmissionLinesProj40FAULTANALYSISINHVDCProj41RealtimeControlofaMobileRobotProj42ReactivePowerCompensationinRailwaysProj43POWERUPGRADATIONINCOMPOSITEACDCTRANSMISSIONSYSTEMProj44DynamicAnalysisofThreePhaseInductionMotorProj45FuzzyControlledSVCforTransmissionLineLabtestandmeasurementAntennaandWavePropagationExp1Exp2Exp3Exp4Exp5Exp6Exp7Exp8Exp9Exp10Exp11Exp12Exp13Exp14CircuitsimulationandToolsexp1exp2exp3exp4exp5exp6exp7exp8exp9exp1exp2exp3exp4exp5exp6exp7exp8Exp1SSDCExp2SSDCExp3SSDCExp4SSDCExp5SSDCExp6SSDCExp7SSDCExp8SSDCExp9SSDCQuizindexQuestionAnswerAnalogIntegratedCircuitsMainQuestionAnswerDigitalLogiccircuitsMainQuestionAnswerDCcircuitsMainQuestionAnswerDCcircuitanalysisMainQuestionAnswerAnalogCommunicationMainQuestionAnswerComputerOrganizationMainProjectideasArduinoprojectsarduinoprojects