Flip-flop (electronics) - Wikipedia

Classical positive-edge-triggered D flip-flop Flip-flop(electronics) FromWikipedia,thefreeencyclopedia Jumptonavigation Jumptosearch Electroniccircuitwithtwostablestates Forotheruses,seeFlip-flop. AnanimatedinteractiveSRlatch(R1,R2=1 kΩ;R3,R4=10 kΩ). Inelectronics,aflip-floporlatchisacircuitthathastwostablestatesandcanbeusedtostorestateinformation–abistablemultivibrator.Thecircuitcanbemadetochangestatebysignalsappliedtooneormorecontrolinputsandwillhaveoneortwooutputs.Itisthebasicstorageelementinsequentiallogic.Flip-flopsandlatchesarefundamentalbuildingblocksofdigitalelectronicssystemsusedincomputers,communications,andmanyothertypesofsystems. Flip-flopsandlatchesareusedasdatastorageelements.Aflip-flopisadevicewhichstoresasinglebit(binarydigit)ofdata;oneofitstwostatesrepresentsa"one"andtheotherrepresentsa"zero".Suchdatastoragecanbeusedforstorageofstate,andsuchacircuitisdescribedassequentiallogicinelectronics.Whenusedinafinite-statemachine,theoutputandnextstatedependnotonlyonitscurrentinput,butalsoonitscurrentstate(andhence,previousinputs).Itcanalsobeusedforcountingofpulses,andforsynchronizingvariably-timedinputsignalstosomereferencetimingsignal. Flip-flopscanbeeitherlevel-triggered(asynchronous,transparentoropaque)oredge-triggered(synchronous,orclocked).Thetermflip-flophashistoricallyreferredgenericallytobothlevel-triggeredandedge-triggeredcircuitsthatstoreasinglebitofdatausinggates.Recently,someauthorsreservethetermflip-flopexclusivelyfordiscussingclockedcircuits;thesimpleonesarecommonlycalledtransparentlatches.[1][2]Usingthisterminology,alevel-sensitiveflip-flopiscalledatransparentlatch,whereasanedge-triggeredflip-flopissimplycalledaflip-flop.Usingeitherterminology,theterm"flip-flop"referstoadevicethatstoresasinglebitofdata,buttheterm"latch"mayalsorefertoadevicethatstoresanynumberofbitsofdatausingasingletrigger.Theterms"edge-triggered",and"level-triggered"maybeusedtoavoidambiguity.[3] Whenalevel-triggeredlatchisenableditbecomestransparent,butanedge-triggeredflip-flop'soutputonlychangesonasingletype(positivegoingornegativegoing)ofclockedge. Contents 1History 2Implementation 3Flip-floptypes 3.1Simpleset-resetlatches 3.1.1SRNORlatch 3.1.2SRNANDlatch 3.1.3SRAND-ORlatch 3.1.4JKlatch 3.2Gatedlatchesandconditionaltransparency 3.2.1GatedSRlatch 3.2.2GatedDlatch 3.2.3Earlelatch 3.3Dflip-flop 3.3.1Classicalpositive-edge-triggeredDflip-flop 3.3.2Master–slaveedge-triggeredDflip-flop 3.3.3Dual-edge-triggeredDflip-flop 3.3.4Edge-triggereddynamicDstorageelement 3.4Tflip-flop 3.5JKflip-flop 4Timingconsiderations 4.1Timingparameters 4.2Metastability 4.3Propagationdelay 5Generalizations 6Seealso 7References 8Externallinks History[edit] Flip-flopschematicsfromtheEcclesandJordanpatentfiled1918,onedrawnasacascadeofamplifierswithapositivefeedbackpath,andtheotherasasymmetriccross-coupledpair Thefirstelectronicflip-flopwasinventedin1918bytheBritishphysicistsWilliamEcclesandF.W.Jordan.[4][5]ItwasinitiallycalledtheEccles–Jordantriggercircuitandconsistedoftwoactiveelements(vacuumtubes).[6]Thedesignwasusedinthe1943BritishColossuscodebreakingcomputer[7]andsuchcircuitsandtheirtransistorizedversionswerecommonincomputersevenaftertheintroductionofintegratedcircuits,thoughflip-flopsmadefromlogicgatesarealsocommonnow.[8][9]Earlyflip-flopswereknownvariouslyastriggercircuitsormultivibrators. AccordingtoP.L.Lindley,anengineerattheUSJetPropulsionLaboratory,theflip-floptypesdetailedbelow(SR,D,T,JK)werefirstdiscussedina1954UCLAcourseoncomputerdesignbyMontgomeryPhister,andthenappearedinhisbookLogicalDesignofDigitalComputers.[10][11]LindleywasatthetimeworkingatHughesAircraftunderEldredNelson,whohadcoinedthetermJKforaflip-flopwhichchangedstateswhenbothinputswereon(alogical"one").TheothernameswerecoinedbyPhister.Theydifferslightlyfromsomeofthedefinitionsgivenbelow.LindleyexplainsthatheheardthestoryoftheJKflip-flopfromEldredNelson,whoisresponsibleforcoiningthetermwhileworkingatHughesAircraft.Flip-flopsinuseatHughesatthetimewereallofthetypethatcametobeknownasJ-K.Indesigningalogicalsystem,Nelsonassignedletterstoflip-flopinputsasfollows:#1:A&B,#2:C&D,#3:E&F,#4:G&H,#5:J&K.Nelsonusedthenotations"j-input"and"k-input"inapatentapplicationfiledin1953.[12] Implementation[edit] Atraditional(simple)flip-flopcircuitbasedonbipolarjunctiontransistors Flip-flopscanbeeithersimple(transparentorasynchronous)orclocked(synchronous).Inthecontextofhardwaredescriptionlanguages,thesimpleonesarecommonlydescribedaslatches,[1]whiletheclockedonesaredescribedasflip-flops.[2] Simpleflip-flopscanbebuiltaroundasinglepairofcross-coupledinvertingelements:vacuumtubes,bipolartransistors,fieldeffecttransistors,inverters,andinvertinglogicgateshaveallbeenusedinpracticalcircuits. Clockeddevicesarespeciallydesignedforsynchronoussystems;suchdevicesignoretheirinputsexceptatthetransitionofadedicatedclocksignal(knownasclocking,pulsing,orstrobing).Clockingcausestheflip-flopeithertochangeortoretainitsoutputsignalbaseduponthevaluesoftheinputsignalsatthetransition.Someflip-flopschangeoutputontherisingedgeoftheclock,othersonthefallingedge. Sincetheelementaryamplifyingstagesareinverting,twostagescanbeconnectedinsuccession(asacascade)toformtheneedednon-invertingamplifier.Inthisconfiguration,eachamplifiermaybeconsideredasanactiveinvertingfeedbacknetworkfortheotherinvertingamplifier.Thusthetwostagesareconnectedinanon-invertingloopalthoughthecircuitdiagramisusuallydrawnasasymmetriccross-coupledpair(boththedrawingsareinitiallyintroducedintheEccles–Jordanpatent). Flip-floptypes[edit] Flip-flopscanbedividedintocommontypes:theSR("set-reset"),D("data"or"delay"[13]),T("toggle"),andJK.Thebehaviorofaparticulartypecanbedescribedbywhatistermedthecharacteristicequation,whichderivesthe"next"(i.e.,afterthenextclockpulse)output,Qnextintermsoftheinputsignal(s)and/orthecurrentoutput, Q {\displaystyleQ} . Simpleset-resetlatches[edit] Whenusingstaticgatesasbuildingblocks,themostfundamentallatchisthesimpleSRlatch,whereSandRstandforsetandreset.Itcanbeconstructedfromapairofcross-coupledNORorNANDlogicgates.ThestoredbitispresentontheoutputmarkedQ. SRNORlatch[edit] AnanimationofaSRlatch,constructedfromapairofcross-coupledNORgates.Redandblackmeanlogical'1'and'0',respectively. AnanimatedSRlatch.Blackandwhitemeanlogical'1'and'0',respectively.S=1,R=0:SetS=0,R=0:HoldS=0,R=1:ResetS=1,R=1:NotallowedTransitioningfromtherestrictedcombination(D)to(A)leadstoanunstablestate. WhiletheRandSinputsarebothlow,feedbackmaintainstheQandQoutputsinaconstantstate,withQthecomplementofQ.IfS(Set)ispulsedhighwhileR(Reset)isheldlow,thentheQoutputisforcedhigh,andstayshighwhenSreturnstolow;similarly,ifRispulsedhighwhileSisheldlow,thentheQoutputisforcedlow,andstayslowwhenRreturnstolow. SRlatchoperation[3] Characteristictable Excitationtable S R Qnext Action Q Qnext S R 0 0 Q Holdstate 0 0 0 X 0 1 0 Reset 0 1 1 0 1 0 1 Set 1 0 0 1 1 1 X Notallowed 1 1 X 0 Note:Xmeansdon'tcare,thatis,either0or1isavalidvalue. TheR=S=1combinationiscalledarestrictedcombinationoraforbiddenstatebecause,asbothNORgatesthenoutputzeros,itbreaksthelogicalequationQ=notQ.Thecombinationisalsoinappropriateincircuitswherebothinputsmaygolowsimultaneously(i.e.atransitionfromrestrictedtokeep).Theoutputwouldlockateither1or0dependingonthepropagationtimerelationsbetweenthegates(aracecondition). HowanSRNORlatchworks. Toovercometherestrictedcombination,onecanaddgatestotheinputsthatwouldconvert(S,R)=(1,1)tooneofthenon-restrictedcombinations.Thatcanbe: Q=1(1,0)–referredtoasanS(dominated)-latch Q=0(0,1)–referredtoasanR(dominated)-latch Thisisdoneinnearlyeveryprogrammablelogiccontroller. Keepstate(0,0)–referredtoasanE-latch Alternatively,therestrictedcombinationcanbemadetotoggletheoutput.TheresultistheJKlatch. ThecharacteristicequationfortheSRlatchis : Q next = R ¯ Q + R ¯ S {\displaystyleQ_{\text{next}}={\bar{R}}Q+{\bar{R}}S} or Q next = R ¯ ( Q + S ) . {\displaystyleQ_{\text{next}}={\bar{R}}(Q+S).} [14] Anotherexpressionis : Q next = S + R ¯ Q {\displaystyleQ_{\text{next}}=S+{\bar{R}}Q} with S R = 0 {\displaystyleSR=0} [15] SRNANDlatch[edit] AnSRlatchconstructedfromcross-coupledNANDgates. ThecircuitshownbelowisabasicNANDlatch.TheinputsaregenerallydesignatedSandRforSetandResetrespectively.BecausetheNANDinputsmustnormallybelogic1toavoidaffectingthelatchingaction,theinputsareconsideredtobeinvertedinthiscircuit(oractivelow). Thecircuitusesfeedbackto"remember"andretainitslogicalstateevenafterthecontrollinginputsignalshavechanged.WhentheSandRinputsarebothhigh,feedbackmaintainstheQoutputstothepreviousstate. SRlatchoperation S R Action 0 0 Q=1,Q=1;notallowed 0 1 Q=1 1 0 Q=0 1 1 Nochange;randominitial SymbolforanSRNANDlatch SRAND-ORlatch[edit] AnSRAND-ORlatch.Lightgreenmeanslogical'1'anddarkgreenmeanslogical'0'.Thelatchiscurrentlyinholdmode(nochange). Fromateachingpointofview,SRlatchesdrawnasapairofcross-coupledcomponents(transistors,gates,tubes,etc.)areoftenhardtounderstandforbeginners.Adidacticallyeasiertounderstandwayistodrawthelatchasasinglefeedbackloopinsteadofthecross-coupling.ThefollowingisanSRlatchbuiltwithanANDgatewithoneinvertedinputandanORgate.Notethattheinverterisnotneededforthelatchfunctionality,butrathertomakebothinputsHigh-active. SRAND-ORlatchoperation S R Action 0 0 Nochange;randominitial 1 0 Q=1 X 1 Q=0 NotethattheSRAND-ORlatchhasthebenefitthatS=1,R=1iswelldefined.InaboveversionoftheSRAND-ORlatchitgivesprioritytotheRsignalovertheSsignal.IfpriorityofSoverRisneeded,thiscanbeachievedbyconnectingoutputQtotheoutputoftheORgateinsteadoftheoutputoftheANDgate. TheSRAND-ORlatchiseasiertounderstand,becausebothgatescanbeexplainedinisolation.WhenneitherSorRisset,thenboththeORgateandtheANDgatearein"holdmode",i.e.,theiroutputistheinputfromthefeedbackloop.WheninputS=1,thentheoutputoftheORgatebecomes1,regardlessoftheotherinputfromthefeedbackloop("setmode").WheninputR=1thentheoutputoftheANDgatebecomes0,regardlessoftheotherinputfromthefeedbackloop("resetmode").AndsincetheoutputQisdirectlyconnectedtotheoutputoftheANDgate,RhaspriorityoverS.Latchesdrawnascross-coupledgatesmaylooklessintuitive,asthebehaviourofonegateappearstobeintertwinedwiththeothergate. NotethattheSRAND-ORlatchcanbetransformedintotheSRNORlatchusinglogictransformations:invertingtheoutputoftheORgateandalsothe2ndinputoftheANDgateandconnectingtheinvertedQoutputbetweenthesetwoaddedinverters;withtheANDgatewithbothinputsinvertedbeingequivalenttoaNORgateaccordingtoDeMorgan'slaws. JKlatch[edit] TheJKlatchismuchlessfrequentlyusedthantheJKflip-flop.TheJKlatchfollowsthefollowingstatetable: JKlatchtruthtable J K Qnext Comment 0 0 Q Nochange 0 1 0 Reset 1 0 1 Set 1 1 Q Toggle Hence,theJKlatchisanSRlatchthatismadetotoggleitsoutput(oscillatebetween0and1)whenpassedtheinputcombinationof11.[16]UnliketheJKflip-flop,the11inputcombinationfortheJKlatchisnotveryusefulbecausethereisnoclockthatdirectstoggling.[17] Gatedlatchesandconditionaltransparency[edit] Latchesaredesignedtobetransparent.Thatis,inputsignalchangescauseimmediatechangesinoutput.Additionallogiccanbeaddedtoasimpletransparentlatchtomakeitnon-transparentoropaquewhenanotherinput(an"enable"input)isnotasserted.Whenseveraltransparentlatchesfolloweachother,usingthesameenablesignal,signalscanpropagatethroughallofthematonce.However,byfollowingatransparent-highlatchwithatransparent-low(oropaque-high)latch,amaster–slaveflip-flopisimplemented. GatedSRlatch[edit] NANDGatedSRLatch(ClockedSRflip-flop).Notetheinvertedinputs. AgatedSRlatchcircuitdiagramconstructedfromANDgates(onleft)andNORgates(onright). AsynchronousSRlatch(sometimesclockedSRflip-flop)canbemadebyaddingasecondlevelofNANDgatestotheinvertedSRlatch(orasecondlevelofANDgatestothedirectSRlatch).TheextraNANDgatesfurtherinverttheinputssoSRlatchbecomesagatedSRlatch(andaSRlatchwouldtransformintoagatedSRlatchwithinvertedenable). WithEhigh(enabletrue),thesignalscanpassthroughtheinputgatestotheencapsulatedlatch;allsignalcombinationsexceptfor(0,0)=holdthenimmediatelyreproduceonthe(Q,Q)output,i.e.thelatchistransparent. WithElow(enablefalse)thelatchisclosed(opaque)andremainsinthestateitwasleftthelasttimeEwashigh. Theenableinputissometimesaclocksignal,butmoreoftenareadorwritestrobe.Whentheenableinputisaclocksignal,thelatchissaidtobelevel-sensitive(totheleveloftheclocksignal),asopposedtoedge-sensitivelikeflip-flopsbelow. GatedSRlatchoperation E/C Action 0 Noaction(keepstate) 1 Thesameasnon-clockedSRlatch SymbolforagatedSRlatch GatedDlatch[edit] Thislatchexploitsthefactthat,inthetwoactiveinputcombinations(01and10)ofagatedSRlatch,RisthecomplementofS.TheinputNANDstageconvertsthetwoDinputstates(0and1)tothesetwoinputcombinationsforthenextSRlatchbyinvertingthedatainputsignal.Thelowstateoftheenablesignalproducestheinactive"11"combination.ThusagatedD-latchmaybeconsideredasaone-inputsynchronousSRlatch.Thisconfigurationpreventsapplicationoftherestrictedinputcombination.Itisalsoknownastransparentlatch,datalatch,orsimplygatedlatch.Ithasadatainputandanenablesignal(sometimesnamedclock,orcontrol).Thewordtransparentcomesfromthefactthat,whentheenableinputison,thesignalpropagatesdirectlythroughthecircuit,fromtheinputDtotheoutputQ.GatedD-latchesarealsolevel-sensitivewithrespecttotheleveloftheclockorenablesignal. TransparentlatchesaretypicallyusedasI/Oportsorinasynchronoussystems,orinsynchronoustwo-phasesystems(synchronoussystemsthatuseatwo-phaseclock),wheretwolatchesoperatingondifferentclockphasespreventdatatransparencyasinamaster–slaveflip-flop. Latchesareavailableasintegratedcircuits,usuallywithmultiplelatchesperchip.Forexample,74HC75isaquadrupletransparentlatchinthe7400series. Thetruthtablebelowshowsthatwhentheenable/clockinputis0,theDinputhasnoeffectontheoutput.WhenE/Cishigh,theoutputequalsD. GatedDlatchtruthtable E/C D Q Q Comment 0 X Qprev Qprev Nochange 1 0 0 1 Reset 1 1 1 0 Set SymbolforagatedDlatch AgatedDlatchbasedonanSRNANDlatch AgatedDlatchbasedonanSRNORlatch AnanimatedgatedDlatch.Blackandwhitemeanlogical'1'and'0',respectively.D=1,E=1:setD=1,E=0:holdD=0,E=0:holdD=0,E=1:reset AgatedDlatchinpasstransistorlogic,similartotheonesintheCD4042ortheCD74HC75integratedcircuits. Earlelatch[edit] Theclassicgatedlatchdesignshavesomeundesirablecharacteristics.[18]Theyrequiredouble-raillogicoraninverter.Theinput-to-outputpropagationmaytakeuptothreegatedelays.Theinput-to-outputpropagationisnotconstant–someoutputstaketwogatedelayswhileotherstakethree. Designerslookedforalternatives.[19]AsuccessfulalternativeistheEarlelatch.Itrequiresonlyasingledatainput,anditsoutputtakesaconstanttwogatedelays.Inaddition,thetwogatelevelsoftheEarlelatchcan,insomecases,bemergedwiththelasttwogatelevelsofthecircuitsdrivingthelatchbecausemanycommoncomputationalcircuitshaveanORlayerfollowedbyanANDlayerastheirlasttwolevels.Mergingthelatchfunctioncanimplementthelatchwithnoadditionalgatedelays.[18]Themergeiscommonlyexploitedinthedesignofpipelinedcomputers,and,infact,wasoriginallydevelopedbyJohnG.EarletobeusedintheIBMSystem/360Model91forthatpurpose.[20] TheEarlelatchishazardfree.[21]IfthemiddleNANDgateisomitted,thenonegetsthepolarityholdlatch,whichiscommonlyusedbecauseitdemandslesslogic.[21][22]However,itissusceptibletologichazard.Intentionallyskewingtheclocksignalcanavoidthehazard.[22] Earlelatchusescomplementaryenableinputs:enableactivelow(E_L)andenableactivehigh(E_H) AnanimatedEarlelatch.Blackandwhitemeanlogical'1'and'0',respectively.D=1,E_H=1:setD=0,E_H=1:resetD=1,E_H=0:hold Dflip-flop[edit] Dflip-flopsymbol TheDflip-flopiswidelyused.Itisalsoknownasa"data"or"delay"flip-flop. TheDflip-flopcapturesthevalueoftheD-inputatadefiniteportionoftheclockcycle(suchastherisingedgeoftheclock).ThatcapturedvaluebecomestheQoutput.Atothertimes,theoutputQdoesnotchange.[23][24]TheDflip-flopcanbeviewedasamemorycell,azero-orderhold,oradelayline.[25] Truthtable: Clock D Qnext Risingedge 0 0 Risingedge 1 1 Non-rising X Q (Xdenotesadon'tcarecondition,meaningthesignalisirrelevant) MostD-typeflip-flopsinICshavethecapabilitytobeforcedtothesetorresetstate(whichignorestheDandclockinputs),muchlikeanSRflip-flop.Usually,theillegalS=R=1conditionisresolvedinD-typeflip-flops.SettingS=R=0makestheflip-flopbehaveasdescribedabove.HereisthetruthtablefortheotherpossibleSandRconfigurations: Inputs Outputs S R D > Q Q 0 1 X X 0 1 1 0 X X 1 0 1 1 X X 1 1 4-bitserial-in,parallel-out(SIPO)shiftregister Theseflip-flopsareveryuseful,astheyformthebasisforshiftregisters,whichareanessentialpartofmanyelectronicdevices.TheadvantageoftheDflip-flopovertheD-type"transparentlatch"isthatthesignalontheDinputpiniscapturedthemomenttheflip-flopisclocked,andsubsequentchangesontheDinputwillbeignoreduntilthenextclockevent.Anexceptionisthatsomeflip-flopshavea"reset"signalinput,whichwillresetQ(tozero),andmaybeeitherasynchronousorsynchronouswiththeclock. Theabovecircuitshiftsthecontentsoftheregistertotheright,onebitpositiononeachactivetransitionoftheclock.TheinputXisshiftedintotheleftmostbitposition. Classicalpositive-edge-triggeredDflip-flop[edit] AfewdifferenttypesofedgetriggeredDflip‑flopsApositive-edge-triggeredDflip-flopApositive-edge-triggeredDflip-flopwithsetandreset Thiscircuit[26]consistsoftwostagesimplementedbySRNANDlatches.Theinputstage(thetwolatchesontheleft)processestheclockanddatasignalstoensurecorrectinputsignalsfortheoutputstage(thesinglelatchontheright).Iftheclockislow,boththeoutputsignalsoftheinputstagearehighregardlessofthedatainput;theoutputlatchisunaffectedanditstoresthepreviousstate.Whentheclocksignalchangesfromlowtohigh,onlyoneoftheoutputvoltages(dependingonthedatasignal)goeslowandsets/resetstheoutputlatch:ifD=0,theloweroutputbecomeslow;ifD=1,theupperoutputbecomeslow.Iftheclocksignalcontinuesstayinghigh,theoutputskeeptheirstatesregardlessofthedatainputandforcetheoutputlatchtostayinthecorrespondingstateastheinputlogicalzero(oftheoutputstage)remainsactivewhiletheclockishigh.Hencetheroleoftheoutputlatchistostorethedataonlywhiletheclockislow. ThecircuitiscloselyrelatedtothegatedDlatchasboththecircuitsconvertthetwoDinputstates(0and1)totwoinputcombinations(01and10)fortheoutputSRlatchbyinvertingthedatainputsignal(boththecircuitssplitthesingleDsignalintwocomplementarySandRsignals).ThedifferenceisthatinthegatedDlatchsimpleNANDlogicalgatesareusedwhileinthepositive-edge-triggeredDflip-flopSRNANDlatchesareusedforthispurpose.Theroleoftheselatchesisto"lock"theactiveoutputproducinglowvoltage(alogicalzero);thusthepositive-edge-triggeredDflip-flopcanalsobethoughtofasagatedDlatchwithlatchedinputgates. Master–slaveedge-triggeredDflip-flop[edit] Amaster–slaveDflip-flop.Itrespondsonthefallingedgeoftheenableinput(usuallyaclock) Animplementationofamaster–slaveDflip-flopthatistriggeredontherisingedgeoftheclock Amaster–slaveDflip-flopiscreatedbyconnectingtwogatedDlatchesinseries,andinvertingtheenableinputtooneofthem.Itiscalledmaster–slavebecausethemasterlatchcontrolstheslavelatch'soutputvalueQandforcestheslavelatchtoholditsvaluewhenevertheslavelatchisenabled,astheslavelatchalwayscopiesitsnewvaluefromthemasterlatchandchangesitsvalueonlyinresponsetoachangeinthevalueofthemasterlatchandclocksignal. Forapositive-edgetriggeredmaster–slaveDflip-flop,whentheclocksignalislow(logical0)the"enable"seenbythefirstor"master"Dlatch(theinvertedclocksignal)ishigh(logical1).Thisallowsthe"master"latchtostoretheinputvaluewhentheclocksignaltransitionsfromlowtohigh.Astheclocksignalgoeshigh(0to1)theinverted"enable"ofthefirstlatchgoeslow(1to0)andthevalueseenattheinputtothemasterlatchis"locked".Nearlysimultaneously,thetwiceinverted"enable"ofthesecondor"slave"Dlatchtransitionsfromlowtohigh(0to1)withtheclocksignal.Thisallowsthesignalcapturedattherisingedgeoftheclockbythenow"locked"masterlatchtopassthroughthe"slave"latch.Whentheclocksignalreturnstolow(1to0),theoutputofthe"slave"latchis"locked",andthevalueseenatthelastrisingedgeoftheclockisheldwhilethe"master"latchbeginstoacceptnewvaluesinpreparationforthenextrisingclockedge. RemovingtheleftmostinverterinthecircuitcreatesaD-typeflip-flopthatstrobesonthefallingedgeofaclocksignal.Thishasatruthtablelikethis: D Q > Qnext 0 X Falling 0 1 X Falling 1 Dual-edge-triggeredDflip-flop[edit] Animplementationofadual-edge-triggeredDflip-flop Flip-Flopsthatreadinanewvalueontherisingandthefallingedgeoftheclockarecalleddual-edge-triggeredflip-flops.Suchaflip-flopmaybebuiltusingtwosingle-edge-triggeredD-typeflip-flopsandamultiplexerasshownintheimage. Circuitsymbolofadual-edge-triggeredDflip-flop Edge-triggereddynamicDstorageelement[edit] ACMOSICimplementationofadynamicedge-triggeredflip-flopwithreset AnefficientfunctionalalternativetoaDflip-flopcanbemadewithdynamiccircuits(whereinformationisstoredinacapacitance)aslongasitisclockedoftenenough;whilenotatrueflip-flop,itisstillcalledaflip-flopforitsfunctionalrole.Whilethemaster–slaveDelementistriggeredontheedgeofaclock,itscomponentsareeachtriggeredbyclocklevels.The"edge-triggeredDflip-flop",asitiscalledeventhoughitisnotatrueflip-flop,doesnothavethemaster–slaveproperties. Edge-triggeredDflip-flopsareoftenimplementedinintegratedhigh-speedoperationsusingdynamiclogic.Thismeansthatthedigitaloutputisstoredonparasiticdevicecapacitancewhilethedeviceisnottransitioning.Thisdesignofdynamicflipflopsalsoenablessimpleresettingsincetheresetoperationcanbeperformedbysimplydischargingoneormoreinternalnodes.Acommondynamicflip-flopvarietyisthetruesingle-phaseclock(TSPC)typewhichperformstheflip-flopoperationwithlittlepowerandathighspeeds.However,dynamicflip-flopswilltypicallynotworkatstaticorlowclockspeeds:givenenoughtime,leakagepathsmaydischargetheparasiticcapacitanceenoughtocausetheflip-floptoenterinvalidstates. Tflip-flop[edit] AcircuitsymbolforaT-typeflip-flop IftheTinputishigh,theTflip-flopchangesstate("toggles")[27]whenevertheclockinputisstrobed.IftheTinputislow,theflip-flopholdsthepreviousvalue.Thisbehaviorisdescribedbythecharacteristicequation: Q next = T ⊕ Q = T Q ¯ + T ¯ Q {\displaystyleQ_{\text{next}}=T\oplusQ=T{\overline{Q}}+{\overline{T}}Q} (expandingtheXORoperator) andcanbedescribedinatruthtable: Tflip-flopoperation[28] Characteristictable Excitationtable T {\displaystyleT} Q {\displaystyleQ} Q next {\displaystyleQ_{\text{next}}} Comment Q {\displaystyleQ} Q next {\displaystyleQ_{\text{next}}} T {\displaystyleT} Comment 0 0 0 Holdstate(noclock) 0 0 0 Nochange 0 1 1 Holdstate(noclock) 1 1 0 Nochange 1 0 1 Toggle 0 1 1 Complement 1 1 0 Toggle 1 0 1 Complement WhenTisheldhigh,thetoggleflip-flopdividestheclockfrequencybytwo;thatis,ifclockfrequencyis4 MHz,theoutputfrequencyobtainedfromtheflip-flopwillbe2 MHz.This"divideby"featurehasapplicationinvarioustypesofdigitalcounters.ATflip-flopcanalsobebuiltusingaJKflip-flop(J&KpinsareconnectedtogetherandactasT)oraDflip-flop(TinputXORQpreviousdrivestheDinput). JKflip-flop[edit] Acircuitsymbolforapositive-edge-triggeredJKflip-flop JKflip-floptimingdiagram TheJKflip-flopaugmentsthebehavioroftheSRflip-flop(J:Set,K:Reset)byinterpretingtheJ=K=1conditionasa"flip"ortogglecommand.Specifically,thecombinationJ=1,K=0isacommandtosettheflip-flop;thecombinationJ=0,K=1isacommandtoresettheflip-flop;andthecombinationJ=K=1isacommandtotoggletheflip-flop,i.e.,changeitsoutputtothelogicalcomplementofitscurrentvalue.SettingJ=K=0maintainsthecurrentstate.TosynthesizeaDflip-flop,simplysetKequaltothecomplementofJ(inputJwillactasinputD).Similarly,tosynthesizeaTflip-flop,setKequaltoJ.TheJKflip-flopisthereforeauniversalflip-flop,becauseitcanbeconfiguredtoworkasanSRflip-flop,aDflip-flop,oraTflip-flop. ThecharacteristicequationoftheJKflip-flopis: Q next = J Q ¯ + K ¯ Q {\displaystyleQ_{\text{next}}=J{\overline{Q}}+{\overline{K}}Q} andthecorrespondingtruthtableis: JKflip-flopoperation[28] Characteristictable Excitationtable J K Comment Qnext Q Qnext Comment J K 0 0 Holdstate Q 0 0 Nochange 0 X 0 1 Reset 0 0 1 Set 1 X 1 0 Set 1 1 0 Reset X 1 1 1 Toggle Q 1 1 Nochange X 0 Timingconsiderations[edit] Timingparameters[edit] Flip-flopsetup,holdandclock-to-outputtimingparameters Theinputmustbeheldsteadyinaperiodaroundtherisingedgeoftheclockknownastheaperture.Imaginetakingapictureofafrogonalily-pad.[29]Supposethefrogthenjumpsintothewater.Ifyoutakeapictureofthefrogasitjumpsintothewater,youwillgetablurrypictureofthefrogjumpingintothewater—it'snotclearwhichstatethefrogwasin.Butifyoutakeapicturewhilethefrogsitssteadilyonthepad(orissteadilyinthewater),youwillgetaclearpicture.Inthesameway,theinputtoaflip-flopmustbeheldsteadyduringtheapertureoftheflip-flop. Setuptimeistheminimumamountoftimethedatainputshouldbeheldsteadybeforetheclockevent,sothatthedataisreliablysampledbytheclock. Holdtimeistheminimumamountoftimethedatainputshouldbeheldsteadyaftertheclockevent,sothatthedataisreliablysampledbytheclock. Apertureisthesumofsetupandholdtime.Thedatainputshouldbeheldsteadythroughoutthistimeperiod.[29] Recoverytimeistheminimumamountoftimetheasynchronoussetorresetinputshouldbeinactivebeforetheclockevent,sothatthedataisreliablysampledbytheclock.Therecoverytimefortheasynchronoussetorresetinputistherebysimilartothesetuptimeforthedatainput. Removaltimeistheminimumamountoftimetheasynchronoussetorresetinputshouldbeinactiveaftertheclockevent,sothatthedataisreliablysampledbytheclock.Theremovaltimefortheasynchronoussetorresetinputistherebysimilartotheholdtimeforthedatainput. Shortimpulsesappliedtoasynchronousinputs(set,reset)shouldnotbeappliedcompletelywithintherecovery-removalperiod,orelseitbecomesentirelyindeterminablewhethertheflip-flopwilltransitiontotheappropriatestate.Inanothercase,whereanasynchronoussignalsimplymakesonetransitionthathappenstofallbetweentherecovery/removaltime,eventuallytheflip-flopwilltransitiontotheappropriatestate,butaveryshortglitchmayormaynotappearontheoutput,dependentonthesynchronousinputsignal.Thissecondsituationmayormaynothavesignificancetoacircuitdesign. SetandReset(andother)signalsmaybeeithersynchronousorasynchronousandthereforemaybecharacterizedwitheitherSetup/HoldorRecovery/Removaltimes,andsynchronicityisverydependentonthedesignoftheflip-flop. DifferentiationbetweenSetup/HoldandRecovery/Removaltimesisoftennecessarywhenverifyingthetimingoflargercircuitsbecauseasynchronoussignalsmaybefoundtobelesscriticalthansynchronoussignals.Thedifferentiationofferscircuitdesignerstheabilitytodefinetheverificationconditionsforthesetypesofsignalsindependently. Metastability[edit] Mainarticle:Metastabilityinelectronics Flip-flopsaresubjecttoaproblemcalledmetastability,whichcanhappenwhentwoinputs,suchasdataandclockorclockandreset,arechangingataboutthesametime.Whentheorderisnotclear,withinappropriatetimingconstraints,theresultisthattheoutputmaybehaveunpredictably,takingmanytimeslongerthannormaltosettletoonestateortheother,orevenoscillatingseveraltimesbeforesettling.Theoretically,thetimetosettledownisnotbounded.Inacomputersystem,thismetastabilitycancausecorruptionofdataoraprogramcrashifthestateisnotstablebeforeanothercircuitusesitsvalue;inparticular,iftwodifferentlogicalpathsusetheoutputofaflip-flop,onepathcaninterpretitasa0andtheotherasa1whenithasnotresolvedtostablestate,puttingthemachineintoaninconsistentstate.[30] Themetastabilityinflip-flopscanbeavoidedbyensuringthatthedataandcontrolinputsareheldvalidandconstantforspecifiedperiodsbeforeandaftertheclockpulse,calledthesetuptime(tsu)andtheholdtime(th)respectively.Thesetimesarespecifiedinthedatasheetforthedevice,andaretypicallybetweenafewnanosecondsandafewhundredpicosecondsformoderndevices.Dependingupontheflip-flop'sinternalorganization,itispossibletobuildadevicewithazero(orevennegative)setuporholdtimerequirementbutnotbothsimultaneously. Unfortunately,itisnotalwayspossibletomeetthesetupandholdcriteria,becausetheflip-flopmaybeconnectedtoareal-timesignalthatcouldchangeatanytime,outsidethecontrolofthedesigner.Inthiscase,thebestthedesignercandoistoreducetheprobabilityoferrortoacertainlevel,dependingontherequiredreliabilityofthecircuit.Onetechniqueforsuppressingmetastabilityistoconnecttwoormoreflip-flopsinachain,sothattheoutputofeachonefeedsthedatainputofthenext,andalldevicesshareacommonclock.Withthismethod,theprobabilityofametastableeventcanbereducedtoanegligiblevalue,butnevertozero.Theprobabilityofmetastabilitygetscloserandclosertozeroasthenumberofflip-flopsconnectedinseriesisincreased.Thenumberofflip-flopsbeingcascadedisreferredtoasthe"ranking";"dual-ranked"flipflops(twoflip-flopsinseries)isacommonsituation. So-calledmetastable-hardenedflip-flopsareavailable,whichworkbyreducingthesetupandholdtimesasmuchaspossible,buteventhesecannoteliminatetheproblementirely.Thisisbecausemetastabilityismorethansimplyamatterofcircuitdesign.Whenthetransitionsintheclockandthedataareclosetogetherintime,theflip-flopisforcedtodecidewhicheventhappenedfirst.Howeverfastthedeviceismade,thereisalwaysthepossibilitythattheinputeventswillbesoclosetogetherthatitcannotdetectwhichonehappenedfirst.Itisthereforelogicallyimpossibletobuildaperfectlymetastable-proofflip-flop.Flip-flopsaresometimescharacterizedforamaximumsettlingtime(themaximumtimetheywillremainmetastableunderspecifiedconditions).Inthiscase,dual-rankedflip-flopsthatareclockedslowerthanthemaximumallowedmetastabilitytimewillprovideproperconditioningforasynchronous(e.g.,external)signals. Propagationdelay[edit] Anotherimportanttimingvalueforaflip-flopistheclock-to-outputdelay(commonsymbolindatasheets:tCO)orpropagationdelay(tP),whichisthetimeaflip-floptakestochangeitsoutputaftertheclockedge.Thetimeforahigh-to-lowtransition(tPHL)issometimesdifferentfromthetimeforalow-to-hightransition(tPLH). Whencascadingflip-flopswhichsharethesameclock(asinashiftregister),itisimportanttoensurethatthetCOofaprecedingflip-flopislongerthantheholdtime(th)ofthefollowingflip-flop,sodatapresentattheinputofthesucceedingflip-flopisproperly"shiftedin"followingtheactiveedgeoftheclock.ThisrelationshipbetweentCOandthisnormallyguaranteediftheflip-flopsarephysicallyidentical.Furthermore,forcorrectoperation,itiseasytoverifythattheclockperiodhastobegreaterthanthesumtsu + th. Generalizations[edit] Flip-flopscanbegeneralizedinatleasttwoways:bymakingthem1-of-Ninsteadof1-of-2,andbyadaptingthemtologicwithmorethantwostates.Inthespecialcasesof1-of-3encoding,ormulti-valuedternarylogic,suchanelementmaybereferredtoasaflip-flap-flop.[31] Inaconventionalflip-flop,exactlyoneofthetwocomplementaryoutputsishigh.ThiscanbegeneralizedtoamemoryelementwithNoutputs,exactlyoneofwhichishigh(alternatively,whereexactlyoneofNislow).Theoutputisthereforealwaysaone-hot(respectivelyone-cold)representation.Theconstructionissimilartoaconventionalcross-coupledflip-flop;eachoutput,whenhigh,inhibitsalltheotheroutputs.[32]Alternatively,moreorlessconventionalflip-flopscanbeused,oneperoutput,withadditionalcircuitrytomakesureonlyoneatatimecanbetrue.[33] Anothergeneralizationoftheconventionalflip-flopisamemoryelementformulti-valuedlogic.Inthiscasethememoryelementretainsexactlyoneofthelogicstatesuntilthecontrolinputsinduceachange.[34]Inaddition,amultiple-valuedclockcanalsobeused,leadingtonewpossibleclocktransitions.[35] Seealso[edit] WikimediaCommonshasmediarelatedtoFlip-flops. Latchingrelay Positivefeedback Pulsetransitiondetector Staticrandom-accessmemory Sampleandhold,analoglatch References[edit] ^abPedroni,VolneiA.(2008).DigitalelectronicsanddesignwithVHDL.MorganKaufmann.p. 329.ISBN 978-0-12-374270-4. ^abLatchesandFlipFlops(EE42/100Lecture24fromBerkeley)"...Sometimesthetermsflip-flopandlatchareusedinterchangeably..." ^abRoth,CharlesH.Jr."LatchesandFlip-Flops."FundamentalsofLogicDesign.Boston:PWS,1995.Print. ^GB148582,Eccles,WilliamHenry&Jordan,FrankWilfred,"Improvementsinionicrelays",published1920-08-05  ^See: W.H.EcclesandF.W.Jordan(19September1919)"Atriggerrelayutilizingthree-electrodethermionicvacuumtubes,"TheElectrician,83 :298. Reprintedin:W.H.EcclesandF.W.Jordan(December1919)"Atriggerrelayutilizingthree-electrodethermionicvacuumtubes,"TheRadioReview,1(3) :143–146. Summaryin:W.H.EcclesandF.W.Jordan(1919)"Atriggerrelayutilisingthreeelectrodethermionicvacuumtubes,"ReportoftheEighty-seventhMeetingoftheBritishAssociationfortheAdvancementofScience:Bournemouth:1919,September9–13,pp.271–272. ^Pugh,EmersonW.;Johnson,LyleR.;Palmer,JohnH.(1991).IBM's360andearly370systems.MITPress.p. 10.ISBN 978-0-262-16123-7. ^Flowers,ThomasH.(1983),"TheDesignofColossus",AnnalsoftheHistoryofComputing,5(3):249,doi:10.1109/MAHC.1983.10079,S2CID 39816473 ^Gates,EarlD.(2000-12-01).Introductiontoelectronics(4th ed.).DelmarThomson(Cengage)Learning.p. 299.ISBN 978-0-7668-1698-5. ^ Fogiel,Max;Gu,You-Liang(1998).TheElectronicsproblemsolver,Volume1(revised ed.).Research&EducationAssoc.p. 1223.ISBN 978-0-87891-543-9. ^P.L.Lindley,Aug.1968,EDN(magazine),(letterdatedJune13,1968). ^ Phister,Montgomery(1958).LogicalDesignofDigitalComputers.Wiley.p. 128.ISBN 9780608102658. ^US2850566,Nelson,EldredC.,"High-speedprintingsystem",published1958-09-02,assignedtoHughesAircraftCo.  ^ Shiva,SajjanG.(2000).Computerdesignandarchitecture(3rd ed.).CRCPress.p. 81.ISBN 978-0-8247-0368-4. ^ Langholz,Gideon;Kandel,Abraham;Mott,JoeL.(1998).FoundationsofDigitalLogicDesign.Singapore:WorldScientificPublishingCo.Ptc.Ltd.p. 344.ISBN 978-981-02-3110-1. ^"SummaryoftheTypesofFlip-flopBehaviour".Retrievedon16April2018. ^Hinrichsen,Diederich;Pritchard,AnthonyJ.(2006).MathematicalSystemsTheoryI:Modelling,StateSpaceAnalysis,StabilityandRobustness.Springer.pp. 63–64.ISBN 9783540264101. ^Farhat,HassanA.(2004).Digitaldesignandcomputerorganization.Vol. 1.CRCPress.p. 274.ISBN 978-0-8493-1191-8. ^abKogge,PeterM.(1981).TheArchitectureofPipelinedComputers.McGraw-Hill.pp. 25–27.ISBN 0-07-035237-2. ^ Cotten,L.W.(1965)."CircuitImplementationofHigh-SpeedPipelineSystems".AFIPSProc.FallJointComputerConference:489–504.doi:10.1145/1463891.1463945.S2CID 15955626. ^ Earle,JohnG.(March1965)."LatchedCarry-SaveAdder".IBMTechnicalDisclosureBulletin.7(10):909–910. ^ab Omondi,AmosR.(1999-04-30).TheMicroarchitectureofPipelinedandSuperscalarComputers.Springer.pp. 40–42.ISBN 978-0-7923-8463-2. ^ab Kunkel,StevenR.;Smith,JamesE.(May1986)."OptimalPipelininginSupercomputers".ACMSIGARCHComputerArchitectureNews.ACM.14(2):404–411[406].CiteSeerX 10.1.1.99.2773.doi:10.1145/17356.17403.ISSN 0163-5964.S2CID 2733845. ^TheDFlip-Flop ^"Edge-TriggeredFlip-flops".Archivedfromtheoriginalon2013-09-08.Retrieved2011-12-15. ^ASurveyofDigitalComputerMemorySystems ^SN7474TIdatasheet ^"UnderstandingtheTFlip-Flop".oemsecrets.com.Retrieved29April2021. ^ab Mano,M.Morris;Kime,CharlesR.(2004).LogicandComputerDesignFundamentals,3rdEdition.UpperSaddleRiver,NJ,USA:PearsonEducationInternational.p. 283.ISBN 0-13-191165-1. ^abHarris,S;Harris,D(2016).DigitalDesignandComputerArchitecture-ARMEdition.MorganKaufmann,Waltham,MA.ISBN 978-0-12-800056-4. ^ Chaney,ThomasJ.;Molnar,CharlesE.(April1973)."AnomalousBehaviorofSynchronizerandArbiterCircuits".IEEETransactionsonComputers.C-22(4):421–422.doi:10.1109/T-C.1973.223730.ISSN 0018-9340.S2CID 12594672. ^OftenattributedtoDonKnuth(1969)(seeMidhatJ.Gazalé(2000).Number:fromAhmestoCantor.PrincetonUniversityPress.p. 57.ISBN 978-0-691-00515-7.),thetermflip-flap-flopactuallyappearedmuchearlierinthecomputingliterature,forexample, Bowdon,EdwardK.(1960).Thedesignandapplicationofa"flip-flap-flop"usingtunneldiodes(Master'sthesis).UniversityofNorthDakota.,andin Alexander,W.(Feb1964)."Theternarycomputer".ElectronicsandPower.IET.10(2):36–39.doi:10.1049/ep.1964.0037. ^"Ternary"flip-flap-flop"".Archivedfromtheoriginalon2009-01-05.Retrieved2009-10-17. ^US6975152,Lapidus,PeterD.,"Flipflopsupportingglitchlessoperationonaone-hotbusandmethod",published2005-12-13,assignedtoAdvancedMicroDevicesInc.  ^ Irving,ThurmanA.;Shiva,SajjanG.;Nagle,H.Troy(March1976)."Flip-FlopsforMultiple-ValuedLogic".IEEETransactionsonComputers.C-25(3):237–246.doi:10.1109/TC.1976.5009250.S2CID 34323423. ^ Wu,Haomin;ZhuangNan(1991)."Researchintoternaryedge-triggeredJKLflip-flop".JournalofElectronics(China).8(Volume8,Number3/July,1991):268–275.doi:10.1007/BF02778378.S2CID 61275953. Externallinks[edit] Wikibookshasabookonthetopicof:DigitalCircuits/Flip-Flops FlipFlopHierarchyArchived2015-04-08attheWaybackMachine,showsinteractiveflipflopcircuits. TheJ-KFlip-Flop vteDigitalelectronicsComponents Transistor Resistor Inductor Capacitor Printedelectronics Printedcircuitboard Electroniccircuit Flip-flop Memorycell Combinationallogic Sequentiallogic Logicgate Booleancircuit Integratedcircuit(IC) Hybridintegratedcircuit(HIC) Mixed-signalintegratedcircuit Three-dimensionalintegratedcircuit(3DIC) Emitter-coupledlogic(ECL) Erasableprogrammablelogicdevice(EPLD) Macrocellarray Programmablelogicarray(PLA) Programmablelogicdevice(PLD) ProgrammableArrayLogic(PAL) Genericarraylogic(GAL) Complexprogrammablelogicdevice(CPLD) Field-programmablegatearray(FPGA) Field-programmableobjectarray(FPOA) Application-specificintegratedcircuit(ASIC) TensorProcessingUnit(TPU) Theory Digitalsignal Booleanalgebra Logicsynthesis Logicincomputerscience Computerarchitecture Digitalsignal Digitalsignalprocessing Circuitminimization Switchingcircuittheory Gateequivalent Design Logicsynthesis Placeandroute Placement Routing Register-transferlevel Hardwaredescriptionlanguage High-levelsynthesis Formalequivalencechecking Synchronouslogic Asynchronouslogic Finite-statemachine Hierarchicalstatemachine Applications Computerhardware Hardwareacceleration Digitalaudio radio Digitalphotography Digitaltelephone Digitalvideo cinematography television Electronicliterature Designissues Metastability Runtpulse Authoritycontrol:Nationallibraries Germany Retrievedfrom"https://en.wikipedia.org/w/index.php?title=Flip-flop_(electronics)&oldid=1097261795" Categories:Computer-relatedintroductionsin1918DigitalelectronicsElectronicengineeringDigitalsystemsLogicgatesComputermemoryHiddencategories:ArticleswithshortdescriptionShortdescriptionisdifferentfromWikidataCommonscategorylinkisonWikidataWebarchivetemplatewaybacklinksArticleswithGNDidentifiers Navigationmenu Personaltools NotloggedinTalkContributionsCreateaccountLogin Namespaces ArticleTalk English Views ReadEditViewhistory More Search Navigation MainpageContentsCurrenteventsRandomarticleAboutWikipediaContactusDonate Contribute HelpLearntoeditCommunityportalRecentchangesUploadfile Tools WhatlinkshereRelatedchangesUploadfileSpecialpagesPermanentlinkPageinformationCitethispageWikidataitem Print/export DownloadasPDFPrintableversion Inotherprojects WikimediaCommonsWikibooksWikiversity Languages العربيةAsturianuAzərbaycancaবাংলাБеларускаяБългарскиBosanskiCatalàČeštinaDanskDeutschEestiΕλληνικάEspañolEuskaraفارسیFrançais한국어हिन्दीHrvatskiBahasaIndonesiaItalianoעבריתҚазақшаКыргызчаLatviešuLombardMagyarМакедонскиMalagasyമലയാളംNederlands日本語NorskbokmålPolskiPortuguêsRomânăРусскийසිංහලSimpleEnglishSlovenčinaSlovenščinaСрпски/srpskiSuomiSvenskaไทยТоҷикӣTürkçeУкраїнськаTiếngViệt吴语粵語中文 Editlinks