JK Flip Flop and the Master-Slave JK Flip Flop Tutorial

The JK flip flop is basically a gated SR flip-flop with the addition of a clock input circuitry that prevents the illegal or invalid output condition that can ... X Registertodownloadpremiumcontent! Registertodownloadpremiumcontent! X Deutsch Polski Register LogIn ACCircuits Amplifiers Attenuators BinaryNumbers BooleanAlgebra Capacitors CombinationalLogic Connectivity Counters DCCircuits Diodes Electromagnetism Filters Inductors Input/OutputDevices LogicGates MiscellaneousCircuits OperationalAmplifiers Oscillator PowerElectronics PowerSupplies Premium RCNetworks Resistors Resources SequentialLogic Systems Transformers Transistors Uncategorized WaveformGenerators PremiumContent FurtherEducation Sitemap ContactUs Home / SequentialLogic / TheJKFlipFlop TheJKFlipFlop TheJKFlip-flopissimilartotheSRFlip-flopbutthereisnochangeinstatewhentheJandKinputsarebothLOW ThebasicS-RNANDflip-flopcircuithasmanyadvantagesandusesinsequentiallogiccircuitsbutitsuffersfromtwobasicswitchingproblems. 1.theSet = 0andReset = 0condition(S = R = 0)mustalwaysbeavoided 2.ifSetorResetchangestatewhiletheenable(EN)inputishighthecorrectlatchingactionmaynotoccur ThentoovercomethesetwofundamentaldesignproblemswiththeSRflip-flopdesign,theJKflipFlopwasdeveloped. ThissimpleJKflipFlopisthemostwidelyusedofalltheflip-flopdesignsandisconsideredtobeauniversalflip-flopcircuit.Thetwoinputslabelled“J”and“K”arenotshortenedabbreviatedlettersofotherwords,suchas“S”forSetand“R”forReset,butarethemselvesautonomousletterschosenbyitsinventorJackKilbytodistinguishtheflip-flopdesignfromothertypes. ThesequentialoperationoftheJKflipflopisexactlythesameasforthepreviousSRflip-flopwiththesame“Set”and“Reset”inputs.Thedifferencethistimeisthatthe“JKflipflop”hasnoinvalidorforbiddeninputstatesoftheSRLatchevenwhenSandRarebothatlogic“1”. TheJKflipflopisbasicallyagatedSRflip-flopwiththeadditionofaclockinputcircuitrythatpreventstheillegalorinvalidoutputconditionthatcanoccurwhenbothinputsSandRareequaltologiclevel“1”.Duetothisadditionalclockedinput,aJKflip-flophasfourpossibleinputcombinations,“logic1”,“logic0”,“nochange”and“toggle”.ThesymbolforaJKflipflopissimilartothatofanSRBistableLatchasseenintheprevioustutorialexceptfortheadditionofaclockinput. TheBasicJKFlip-flop BoththeSandtheRinputsofthepreviousSRbistablehavenowbeenreplacedbytwoinputscalledtheJandKinputs,respectivelyafteritsinventorJackKilby.Thenthisequatesto:J = SandK = R. Thetwo2-inputANDgatesofthegatedSRbistablehavenowbeenreplacedbytwo3-inputNANDgateswiththethirdinputofeachgateconnectedtotheoutputsatQandQ.ThiscrosscouplingoftheSRflip-flopallowsthepreviouslyinvalidconditionofS=“1”andR=“1”statetobeusedtoproducea“toggleaction”asthetwoinputsarenowinterlocked. Ifthecircuitisnow“SET”theJinputisinhibitedbythe“0”statusofQthroughthelowerNANDgate.Ifthecircuitis“RESET”theKinputisinhibitedbythe“0”statusofQthroughtheupperNANDgate.AsQandQarealwaysdifferentwecanusethemtocontroltheinput.WhenbothinputsJandKareequaltologic“1”,theJKflipfloptogglesasshowninthefollowingtruthtable. TheTruthTablefortheJKFunction sameas forthe SRLatch Clock Input Output Description Clk J K Q Q X 0 0 1 0 Memory nochange X 0 0 0 1 ‾↓ ̲ 0 1 1 0 ResetQ»0 X 0 1 0 1 ‾↓ ̲ 1 0 0 1 SetQ»1 X 1 0 1 0 toggle action ‾↓ ̲ 1 1 0 1 Toggle ‾↓ ̲ 1 1 1 0 ThentheJKflip-flopisbasicallyanSRflipflopwithfeedbackwhichenablesonlyoneofitstwoinputterminals,eitherSETorRESETtobeactiveatanyonetimeundernormalswitchingtherebyeliminatingtheinvalidconditionseenpreviouslyintheSRflipflopcircuit. However,ifboththeJandKinputsareHIGHatlogic“1”(J=K=1),whentheclockinputgoesHIGH,thecircuitwill“toggle”asitsoutputsswitchandchangestatecomplementingeachother.ThisresultsintheJKflip-flopactingmorelikeaT-typetoggleflip-flopwhenbothterminalsare“HIGH”.However,astheoutputsarefedbacktotheinputs,thiscancausetheoutputatQtooscillatebetweenSETandRESETcontinuouslyafterbeingcomplementedonce. WhilethisJKflip-flopcircuitisanimprovementontheclockedSRflip-flopitalsosuffersfromtimingproblemscalled“race”iftheoutputQchangesstatebeforethetimingpulseoftheclockinputhastimetogo“OFF”.Toavoidthisthetimingpulseperiod( T )mustbekeptasshortaspossible(highfrequency).AsthisissometimesnotpossiblewithbasicJKflip-flopsbuiltusingbasicNANDorNORgates,farmoreadvancedmaster-slave(edge-triggered)flip-flopsweredevelopedwhicharemorestable. Master-SlaveJKFlip-flop Themaster-slaveflip-flopeliminatesallthetimingproblemsbyusingtwoSRflip-flopsconnectedtogetherinaseriesconfiguration.Oneflip-flopactsasthe“Master”circuit,whichtriggersontheleadingedgeoftheclockpulsewhiletheotheractsasthe“Slave”circuit,whichtriggersonthefallingedgeoftheclockpulse.Thisresultsinthetwosections,themastersectionandtheslavesectionbeingenabledduringoppositehalf-cyclesoftheclocksignal. TheTTL74LS73isaDualJKflip-flopIC,whichcontainstwoindividualJKtypebistable’swithinasinglechipenablingsingleormaster-slavetoggleflip-flopstobemade.OtherJKflipflopIC’sincludethe74LS107DualJKflip-flopwithclear,the74LS109Dualpositive-edgetriggeredJKflipflopandthe74LS112Dualnegative-edgetriggeredflip-flopwithbothpresetandclearinputs. DualJKFlip-flop74LS73 OtherPopularJKFlip-flopICs DeviceNumber Subfamily DeviceDescription 74LS73 LSTTL DualJK-typeFlipFlopswithClear 74LS76 LSTTL DualJK-typeFlipFlopswithPresetandClear 74LS107 LSTTL DualJK-typeFlipFlopswithClear 4027B StandardCMOS DualJK-typeFlipFlop TheMaster-SlaveJKFlip-flop TheMaster-SlaveFlip-FlopisbasicallytwogatedSRflip-flopsconnectedtogetherinaseriesconfigurationwiththeslavehavinganinvertedclockpulse.TheoutputsfromQandQfromthe“Slave”flip-floparefedbacktotheinputsofthe“Master”withtheoutputsofthe“Master”flipflopbeingconnectedtothetwoinputsofthe“Slave”flipflop.Thisfeedbackconfigurationfromtheslave’soutputtothemaster’sinputgivesthecharacteristictoggleoftheJKflipflopasshownbelow. TheMaster-SlaveJKFlipFlop TheinputsignalsJandKareconnectedtothegated“master”SRflipflopwhich“locks”theinputconditionwhiletheclock(Clk)inputis“HIGH”atlogiclevel“1”.Astheclockinputofthe“slave”flipflopistheinverse(complement)ofthe“master”clockinput,the“slave”SRflipflopdoesnottoggle.Theoutputsfromthe“master”flipflopareonly“seen”bythegated“slave”flipflopwhentheclockinputgoes“LOW”tologiclevel“0”. Whentheclockis“LOW”,theoutputsfromthe“master”flipfloparelatchedandanyadditionalchangestoitsinputsareignored.Thegated“slave”flipflopnowrespondstothestateofitsinputspassedoverbythe“master”section. Thenonthe“Low-to-High”transitionoftheclockpulsetheinputsofthe“master”flipfloparefedthroughtothegatedinputsofthe“slave”flipflopandonthe“High-to-Low”transitionthesameinputsarereflectedontheoutputofthe“slave”makingthistypeofflipflopedgeorpulse-triggered. Then,thecircuitacceptsinputdatawhentheclocksignalis“HIGH”,andpassesthedatatotheoutputonthefalling-edgeoftheclocksignal.Inotherwords,theMaster-SlaveJKFlipflopisa“Synchronous”deviceasitonlypassesdatawiththetimingoftheclocksignal. InthenexttutorialaboutSequentialLogicCircuits,wewilllookatMultivibratorsthatareusedaswaveformgeneratorstoproducetheclocksignalstoswitchsequentialcircuits. PreviousSequentialLogicCircuits NextMultivibrators ReadmoreTutorialsinSequentialLogic 1.SequentialLogicCircuits 2.TheJKFlipFlop 3.Multivibrators 4.TheD-typeFlipFlop 5.TheShiftRegister 6.JohnsonRingCounter 7.ConversionofFlip-flops 8.TheToggleFlip-flop 233Comments JointheconversationCancelreplyError!Pleasefillallfields. Notifymeoffollow-upcommentsbyemail. Δ Syamala Icanunderstandeasily PostedonJune14th2022|7:05am Reply SubrataAdhikary It’saveryhelpfully…. PostedonApril27th2022|4:39pm Reply krishnavamsi whatisthedifferencebetweenjkflipflopandmasterrjkflipflop PostedonJanuary24th2022|7:47am Reply Sid Bonjour.J’espèreapprendreetapprofondirmescours.boncourageetmerciencore PostedonJanuary08th2022|10:51am Reply SamuelJonathan Iwanttounderstandsynchronouscounter PostedonNovember29th2021|12:18pm Reply PRITAMSAMANTA Iamnotsatisfiedwithoutthetruthtable PostedonNovember25th2021|4:51pm Reply Lowkey Whatwillhappenincaseofbothpresetandclearbeinghigh….oristhatinvalidbecausetheyswitchbetweeneachothereitherbeinghighorlow?? PostedonAugust25th2021|3:41pm Reply SadiqHassan Nicework PostedonAugust20th2021|4:40pm Reply VamsiKrishnamRaju.Sarikonda Plzzputshortnoteonjk&srFlipflops PostedonJuly22nd2021|4:22am Reply ParkesitDanial IdesignedfourNANDGatesJKFlip-FlopusingProteus,butitdidn’twork.TherearegraymarkingsontheinputandoutputoftheNANDGates. Iaskforhelpsolvingit. Thankyou. PostedonJuly07th2021|8:00am Reply WayneStorr Wedonotuse,andarethereforenotfamiliarwithProteus,sowecannothelpyou. PostedonJuly07th2021|11:26am Reply ParkesitDanial Whatprogramdoyouusetodesignlogiccircuit?Pls.advice. PostedonJuly16th2021|2:18am Reply IshaqMusaishaq Veryinterested PostedonApril05th2021|8:17pm Reply sultan …,[27.03.2114:34]UsingtwoJK-FlipFlopstodesignandimplementadigitalcircuitwiththreeLEDsandoneinput(x)arrangedasshowninthefollowingfigure.ThethreeLEDsmustlightsequentially(onlyoneatatime)onaclockwisedirection(ABC)iftheswitch(X)is“high”(1)andpauseifXis“low”(0).Implementyourdesignbysimulation(Multisim). PostedonMarch27th2021|10:44am Reply SudeepNG JKflipflops PostedonMarch13th2021|9:52am Reply digitalguru Totalgarbage.TheJKflipflopisimpossibletoimplementwith4NANDgates.Tryimplementingthisinanysimulatoranditwillfail. PostedonMarch03rd2021|1:38am Reply MattT ToamendmyearliercommentasIoverlookedthe4gatesbit…The8-gatedesignthatIpointtoworks.Editingthattoa4gatedesigndoesindeedfailatthedefaultspeed.Itcanbemadetoworkbyfiddlingwiththesimulationspeed,but,intheend,thesimulationIpointtodoesnot,infact,provideacounterexampletoyourstatement.(Ideally,bothofmycommentswilljustbedeletedbythemoderatorandthesewillneverbeseen…) PostedonMay02nd2021|7:00am Reply MattT Thisoneworksfine: https://www.falstad.com/circuit MenubarCircuits->SequentialLogic->Flip-flops->J-KFlipFlop.Simulationworksfine. PostedonMay02nd2021|6:49am Reply WayneStorr Simulation,simulation,simulation.Gonearethedaysofactuallybuildingandtestingacircuitonbreadboard,todayitscopy,pasteandsimulate,withoutanyrealunderstandingofwhythesimulationprogramdoeswhatitdoes.Suchisthewayofthemodernhobbyist. PostedonMarch03rd2021|8:12am Reply Rafi GoodeveningsirandMadam.Electronicnewsyullbes. PostedonMarch02nd2021|3:15pm Reply malik howtocompletethetableplzhelpme J|K|Y|Y’Q|Q’ 11 10 01 00 PostedonJanuary29th2021|3:33pm Reply Humera Ithelpedmuch,aseverytopicisdescribedinverywellmannerandperfect💯.Andwasmadeeasytounderstandandlearn.Thanku PostedonJanuary27th2021|4:20pm Reply Wouanjiornella Thankyou.Pleaseiwillliketodownloadthetutorialifpossible PostedonJanuary18th2021|10:33pm Reply SumitPasi CanweuseNORGATEinmasterslaveflipflop. PostedonDecember25th2020|6:14am Reply Amit Good PostedonDecember22nd2020|6:21am Reply ViewMore ReadmoreTutorialsinSequentialLogic 1.SequentialLogicCircuits 2.TheJKFlipFlop 3.Multivibrators 4.TheD-typeFlipFlop 5.TheShiftRegister 6.JohnsonRingCounter 7.ConversionofFlip-flops 8.TheToggleFlip-flop LookingforDataSheets? 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