Basic CMOS Logic Gates - Technical Articles - EE Power

A NAND gate places two n-channel transistors in series to ground and two p-channel transistors in parallel connected to +V. Only when both ... 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Logicgatesthatarethebasicbuildingblockofdigitalsystemsarecreatedbycombininganumberofn-andp-channeltransistors.ThemostfundamentalconnectionsaretheNOTgate,thetwo-inputNANDgate,andthetwo-inputNORgate.Thisarticleassumesapositivelogic.   TheCMOSInverterorNOTGate ANOTgatereversestheinputlogicstate.Figure1showsaNOTgateemployingtwoseries-connectedenhancement-typeMOSFETS,onen-channel(NMOS)andonep-channel(PMOS).   Figure1.ACMOSNOTgate.   Theinputisconnectedtothegateterminalofthetwotransistors,andtheoutputisconnectedtobothdrainterminals. Applying+V(logic1)totheinput(Vi),transistorQ2is“on,”andtransistorQ1remains“off.”Underthiscondition,theoutputvoltage(Vo)iscloseto0V(logic0). Connectingtheinputtoground(Vi=0V),transistorQ2is“off,”andtransistorQ1is“on.”Now,theoutputvoltageiscloseto+V(logic1). Table1summarizestheseresults.   A Y 0 1 1 0 Table1.ThetruthtableforaNOTcircuit.   TheCMOSNANDGate NANDdenotesNOT-AND. Table2showsthetruthtableforaNANDcircuit.   A B Y 0 0 1 0 1 1 1 0 1 1 1 0 Table2.Thetruthtableforatwo-inputNANDcircuit.   Figure2showsaCMOStwo-inputNANDgate.P-channeltransistorsQ1andQ2areconnectedinparallelbetween+Vandtheoutputterminal.N-channeltransistorsQ3andQ4areconnectedinseriesbetweentheoutputterminalandground.   Figure2.ACMOStwo-inputNANDgate.   WithQ3andQ4transistors”on”andQ1andQ2transistors“off,”theoutputisalogic0.Thisconditionhappenswhenbothinputs,AandB,arelogic1,confirmingthelowestrowintheabovetruthtable. Withlogic0ininputsAandB,Q3andQ4transistorsare“off,”andQ1andQ2transistorsare“on,”producingalogic1output.Thisisconsistentwiththefirstrowofthetruthtable. Whenoneoftheinputsisalogic“1”andtheotheroneisalogic“0”,eitherQ3is“off”andQ2is“on”orQ4is“off”andQ1is“on.”Theoutputinbothcasesisalogic“1,”validatingthesecondandthethirdrowsofthetruthtable.   TheNORGate NORsignifiesNOT-OR. Table3showsthetruthtableforaNORcircuit.   A B Y 0 0 1 0 1 0 1 0 0 1 1 0 Table3.Thetruthtableforatwo-inputNORcircuit.   TheoutputofaNORgateislogic1withlogic0inbothinputs.Theoutcomesforotherinputcombinationsarelogic0. Figure3showsaCMOStwo-inputNORgate.P-channeltransistorsQ1andQ2areconnectedinseriesbetween+Vandtheoutputterminal.N-channeltransistorsQ3andQ4areconnectedinparallelbetweentheoutputandground.   Figure3.ACMOStwo-inputNORgate. Whenbothinputs,AandB,arelogic0,Q1andQ2are“on,”andQ3andQ4are“off,”andtheoutputislogic1.Thisconfirmsthefirstrowofthetruthtableabove. Withbothinputslogic1,Q3andQ4are“on,”andQ1andQ2are“off,”producingalogic0outputthatconfirmsthelastrowofthetruthtable. Forthetworemaininginputcombinations,eitherQ1is“off”andQ3is“on”orQ2is“off”andisQ4“on”.Inthesecases,theoutputislogic0whichisconsistentwiththeabovetruthtable.   TheANDGate WecansaythatanANDgateisaNOT-NOT-ANDorNOT-NAND.Then,itisjustaNANDgatefollowedbyaninverter. Table4showsthetruthtableforanANDcircuit.   A B Y 0 0 0 0 1 0 1 0 0 1 1 1 Table4.Thetruthtableforatwo-inputCMOSANDcircuit.   Figure4showsaCMOStwo-inputANDgate.   Figure4.ACMOStwo-inputANDgate.   TheORGate AnORgateisaNOT-NOT-ORorNOT-NOR.Then,itisaNORgatefollowedbyaninverter. Table5showsthetruthtablefortheORcircuit.   A B Y 0 0 0 0 1 1 1 0 1 1 1 1 Table5.Thetruthtableforatwo-inputORcircuit.   Figure5showsaCMOStwo-inputORgate.   Figure5.ACMOStwo-inputORgate.   TheExclusiveOR(XOR)Gate Theoutputofatwo-inputXORcircuitassumesthelogic1stateifoneandonlyoneinputassumesthelogic1state. Anequivalentlogicstatementis:”IfB=1andA=0,orifA=1andB=0,thenY=1.” InBooleannotation, \[Y=\bar{A}B+A\bar{B}\] Table6showsthetruthtableforatwo-inputXORcircuit. A B Y 0 0 0 0 1 1 1 0 1 1 1 0 Table6.Thetruthtableforatwo-inputXORcircuit.   Figure6showsatwo-inputlogicdiagram,andfigure7showsaCMOScircuittosatisfytheBooleanequation.   Figure6.AlogicblockdiagramfortheXORcircuit.   Figure7.ACMOStwo-inputXORgate.   TransistorsQ1,Q2,Q3,andQ4comprisetheNORgate.TransistorsQ5andQ6maketheANDingofinputsAandB,andtransistorQ7suppliestheORingoftheNORoutputwiththeANDedoutput.TransistorsQ8,Q9,andQ10complementthearrangementoftransistorsQ5,Q6,andQ7,invertingtheresult.   AbouttheBasicCMOSLogicGates Combinationsofn-andp-channeltransistorsallowtheconstructionoflogicbuildingblocks. Theinverter,NAND,andNORlogicbuildingblocksarethebackboneofmostdigitallogicfamilies. Twoprimaryconnectionsarethetwo-inputNANDgateandthetwo-inputNORgate. ANANDgateplacestwon-channeltransistorsinseriestogroundandtwop-channeltransistorsinparallelconnectedto+V.Onlywhenbothinputsarelogic1,theoutputgoestologic0. ANORgatearrangestwon-channeltransistorsinparallelsothateitheronecanpulltheoutputtoground(logic0)foralogic1(+V)input.Italsoplacestwop-channeltransistorsinseries,whichmustworktogethertopulltheoutputtologic1forlogic0inbothinputs.Theoutputwillgotologic1onlywhenbothAandBarelogic0. ANDandORgatesareNANDandNORgatesfollowedbyaninverter. AnimportantfunctionthatisoftenneededinlogicdesignistheExclusive-OR(XOR),withtheBooleanexpression. \[Y=\bar{A}B+A\bar{B}\] TheXORisnotaprimarygatebutconstructedbyacombinationofotherlogicgates. RelatedContent DigitalElectronicsBasics:UniversalGates DigitalMultimeterBasics DigitalElectronicsBasics:UnderstandingLogicCircuits DigitalElectronicsBasics:ExclusiveGate,LogicDiagrams,andDeMorganTheorem CMOSimplementationofXOR,XNOR,andTGgates LearnMoreAbout: CMOS N-ChannelMOSFET MOSFETs P-ChannelMOSFET CMOSInverter logicgates digital-logicfamily NOTgate NANDgate Comments 0Comments Logintocomment Loadmorecomments YouMayAlsoLike AmericanSuperconductorWins$70MillionContract byJeffShepard Top10WirelessChargingDevelopmentsin2012 byJeffShepard LowLossThyristorsforHighPowerApplications byJensPrzybilla MultiplythePowerofaBoostConverterwithaVersatilePhaseExpander byVictorKhasiev AdvancedPowerElectronicsCorp.EstablishesUSOperation byJeffShepard WelcomeBack Don'thaveanEEPoweraccount?Createonenow. Forgotyourpassword?Clickhere. SignIn Stayloggedin Orsigninwith Facebook Google LinkedIn GitHub